Removed all comments labelled \'simx64\'

hw/rtl/VX_config.vh

@@ -45,7 +45,6 @@
 `define L1_BLOCK_SIZE ((`L2_ENABLE || `L3_ENABLE) ? 16 : `MEM_BLOCK_SIZE)
 `endif
 
-// simx64
 `ifndef STARTUP_ADDR
 `define STARTUP_ADDR 32'h80000000
 `endif

sim/simx/decode.cpp

@@ -111,11 +111,9 @@ static const char* op_string(const Instr &instr) {
     case 0: return "LBI";
     case 1: return "LHI";
     case 2: return "LW";
-    // simx64
     case 3: return "LD";
     case 4: return "LBU";
     case 5: return "LHU";
-    // simx64
     case 6: return "LWU";
     default:
       std::abort();
@@ -125,12 +123,10 @@ static const char* op_string(const Instr &instr) {
     case 0: return "SB";
     case 1: return "SH";
     case 2: return "SW";
-    // simx64
     case 3: return "SD";
     default:
       std::abort();
     }
-  // simx64
   case Opcode::R_INST_64:
     if (func7 & 0x1){
       switch (func3) {
@@ -151,7 +147,6 @@ static const char* op_string(const Instr &instr) {
           std::abort();
       }
     }
-  // simx64  
   case Opcode::I_INST_64:
     switch (func3) {
       case 0: return "ADDIW";
@@ -182,7 +177,6 @@ static const char* op_string(const Instr &instr) {
       std::abort();
     }
   case Opcode::FENCE: return "FENCE";
-  // simx64
   case Opcode::FL: 
     switch (func3) {
       case 0x1: return "VL";
@@ -259,7 +253,6 @@ static const char* op_string(const Instr &instr) {
       default:
         std::abort();
       }
-    // simx64
     case 0x60: 
       switch (rs2) {
       case 0: return "FCVT.W.S";
@@ -376,7 +369,6 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
 }
 
 Decoder::Decoder(const ArchDef &arch) {
-  // simx64
   inst_s_   = arch.wsize() * 4;
   opcode_s_ = 7;
   reg_s_    = 5;
@@ -435,7 +427,6 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
 
   auto iType = op_it->second.iType;
   if (op == Opcode::FL || op == Opcode::FS) { 
-    // simx64
     if (func3 != 0x2 && func3 != 0x3) {
       iType = InstType::V_TYPE;
     }

sim/simx/execute.cpp

@@ -123,7 +123,6 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
     for (int t = 0; t < num_threads; ++t) {
       if (!tmask_.test(t))
         continue;
-      // simx64
       rddata[t] = (immsrc << 12) & 0xfffffffffffff000;
     }    
     rd_write = true;
@@ -155,7 +154,6 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           break;
         case 1: {
           // RV32M: MULH
-          // simx64
           __int128_t first = sext128((__int128_t)rsdata[t][0], 64);
           __int128_t second = sext128((__int128_t)rsdata[t][1], 64);
           rddata[t] = ((first * second) >> 64) & 0xFFFFFFFFFFFFFFFF;
@@ -163,7 +161,6 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         } break;
         case 2: {
           // RV32M: MULHSU       
-          // simx64       
           __int128_t first = sext128((__int128_t)rsdata[t][0], 64);
           __int128_t second = (__int128_t)rsdata[t][1];
           rddata[t] = ((first * second) >> 64) & 0xFFFFFFFFFFFFFFFF;
@@ -171,7 +168,6 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         } break;
         case 3: {
           // RV32M: MULHU
-          // simx64
           __uint128_t first = (__int128_t)rsdata[t][0];
           __uint128_t second = (__int128_t)rsdata[t][1];
           rddata[t] = ((first * second) >> 64) & 0xFFFFFFFFFFFFFFFF;
@@ -179,7 +175,6 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         } break;
         case 4: {
           // RV32M: DIV
-          // simx64
           DoubleWordI dividen = rsdata[t][0];
           DoubleWordI divisor = rsdata[t][1];
           if (divisor == 0) {
@@ -193,7 +188,6 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         } break;
         case 5: {
           // RV32M: DIVU
-          // simx64
           DoubleWord dividen = rsdata[t][0];
           DoubleWord divisor = rsdata[t][1];
           if (divisor == 0) {
@@ -205,7 +199,6 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         } break;
         case 6: {
           // RV32M: REM
-          // simx64
           DoubleWordI dividen = rsdata[t][0];
           DoubleWordI divisor = rsdata[t][1];
           if (rsdata[t][1] == 0) {

sim/simx/types.h

@@ -13,7 +13,6 @@ namespace vortex {
 typedef uint8_t  Byte;
 typedef uint32_t Word;
 typedef int32_t  WordI;
-// simx64
 typedef uint64_t DoubleWord;
 typedef int64_t DoubleWordI;