regression fixes

ci/regression.sh

@@ -3,31 +3,30 @@
 # exit when any command fails
 set -e
 
+# build sources
 make -s
 
 # coverage tests
-make -C tests/runtime run
+make -C tests/runtime run-rtlsim
-make -C tests/riscv/isa run
+make -C tests/riscv/isa run-rtlsim
-make -C tests/opencl run
+make -C tests/regression run-vlsim
-make -C simX run-tests
+make -C tests/opencl run-vlsim
-
+make -C tests/runtime run-simx
-# basic pipeline stress
+make -C tests/riscv/isa run-simx
-./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm --args="-n128"
+make -C tests/regression run-simx
+make -C tests/opencl run-simx
 
 # warp/threads configurations
-./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=2 --app=demo
 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=8 --app=demo
 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=8 --threads=2 --app=demo
 
 # cores clustering
 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --clusters=1 --app=demo --args="-n1"
-./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=1 --app=demo --args="-n1"
 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1"
 
 # L2/L3
 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1"
 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l3cache --app=demo --args="-n1"
-./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=demo --args="-n1"
 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="-n1"
 
 # build flags
@@ -68,3 +67,6 @@ CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=4 --
 
 # test vlsim memory stress
 CONFIGS="-DMEM_LATENCY=100 -DMEM_RQ_SIZE=4 -DMEM_STALLS_MODULO=4" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=sgemm
+
+# basic pipeline stress
+./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm --args="-n128"

hw/simulate/testbench.cpp

@@ -178,7 +178,7 @@ int main(int argc, char **argv) {
 		parse_args(argc, argv);
 
 		for (auto program : programs) {
-			std::cout << "Running " << program << " ..." << std::endl;
+			std::cout << "Running " << program << "..." << std::endl;
 
 			RAM ram;
 			Simulator simulator;

simX/Makefile

@@ -25,11 +25,6 @@ all: $(PROJECT)
 $(PROJECT): $(SRCS)
 	$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@
 
-run-tests:
-	./test_rv32i.sh
-	./test_rv32f.sh
-	./test_runtime.sh
-
 .depend: $(SRCS)
 	$(CXX) $(CXXFLAGS) -MM $^ > .depend;
 

simX/main.cpp

@@ -77,6 +77,7 @@ int main(int argc, char **argv) {
       }
       if (core->check_ebreak()) {
         exitcode = core->getIRegValue(3);
+        running = false;
         break;
       }
     }

simX/test_runtime.sh

@@ -1,14 +0,0 @@
-#!/bin/bash
-
-set -e
-
-make
-make -C ../tests/runtime/dev
-make -C ../tests/runtime/hello
-make -C ../tests/runtime/nlTest
-make -C ../tests/runtime/simple
-
-./simX -a rv32i -i ../tests/runtime/dev/vx_dev_main.hex
-./simX -a rv32i -i ../tests/runtime/hello/hello.hex
-./simX -a rv32i -i ../tests/runtime/nlTest/vx_nl_main.hex
-./simX -a rv32i -i ../tests/runtime/simple/vx_simple.hex

simX/test_rv32f.sh

@@ -1,38 +0,0 @@
-#!/bin/bash
-
-set -e
-
-make
-
-echo ../tests/riscv/isa/rv32uf-p-fadd.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fadd.hex
-
-echo ../tests/riscv/isa/rv32uf-p-fmadd.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fmadd.hex	
-
-echo ../tests/riscv/isa/rv32uf-p-fmin.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fmin.hex
-
-echo ../tests/riscv/isa/rv32uf-p-fcmp.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fcmp.hex	
-
-echo ../tests/riscv/isa/rv32uf-p-fdst.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-ldst.hex 
-
-echo ../tests/riscv/isa/rv32uf-p-fcvt.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fcvt.hex
-
-echo ../tests/riscv/isa/rv32uf-p-fcvt_w.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fcvt_w.hex
-
-echo ../tests/riscv/isa/rv32uf-p-move.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-move.hex
-
-echo ../tests/riscv/isa/rv32uf-p-recording.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-recoding.hex
-
-echo ../tests/riscv/isa/rv32uf-p-fdiv.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fdiv.hex
-
-echo ../tests/riscv/isa/rv32uf-p-fclass.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fclass.hex

simX/test_rv32i.sh

@@ -1,143 +0,0 @@
-#!/bin/bash
-
-set -e
-
-make
-
-echo ./../tests/riscv/isa/rv32ui-p-add.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-add.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-addi.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-addi.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-and.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-and.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-andi.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-andi.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-auipc.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-auipc.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-beq.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-beq.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-bge.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bge.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-bgeu.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bgeu.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-blt.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-blt.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-bltu.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bltu.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-bne.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bne.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-jal.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-jal.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-jalr.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-jalr.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-lb.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lb.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-lbu.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lbu.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-lh.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lh.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-lhu.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lhu.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-lui.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lui.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-lw.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lw.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-or.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-or.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-ori.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-ori.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-sb.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sb.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-sh.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sh.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-simple.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-simple.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-sll.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sll.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-slli.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-slli.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-slt.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-slt.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-slti.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-slti.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-sltiu.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sltiu.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-sltu.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sltu.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-sra.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sra.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-srai.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-srai.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-srl.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-srl.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-srli.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-srli.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-sub.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sub.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-sw.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sw.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-xor.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-xor.hex
-
-echo ./../tests/riscv/isa/rv32ui-p-xori.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-xori.hex
-
-echo ./../tests/riscv/isa/rv32um-p-div.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-div.hex
-
-echo ./../tests/riscv/isa/rv32um-p-divu.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-divu.hex
-
-echo ./../tests/riscv/isa/rv32um-p-mul.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mul.hex
-
-echo ./../tests/riscv/isa/rv32um-p-mulh.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mulh.hex
-
-echo ./../tests/riscv/isa/rv32um-p-mulhsu.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mulhsu.hex
-
-echo ./../tests/riscv/isa/rv32um-p-mulhu.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mulhu.hex
-
-echo ./../tests/riscv/isa/rv32um-p-rem.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-rem.hex
-
-echo ./../tests/riscv/isa/rv32um-p-remu.hex
-./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-remu.hex

tests/opencl/Makefile

@@ -8,7 +8,17 @@ all:
 	$(MAKE) -C printf
 	$(MAKE) -C psort
 	
-run:
+run-simx:
+	$(MAKE) -C vecadd run-simx 
+	$(MAKE) -C sgemm run-simx
+	$(MAKE) -C saxpy run-simx
+	$(MAKE) -C sfilter run-simx
+	$(MAKE) -C nearn run-simx
+	$(MAKE) -C guassian run-simx
+	$(MAKE) -C printf run-simx
+    #$(MAKE) -C psort run-simx
+
+run-vlsim:
 	$(MAKE) -C vecadd run-vlsim 
 	$(MAKE) -C sgemm run-vlsim
 	$(MAKE) -C saxpy run-vlsim
@@ -16,7 +26,7 @@ run:
 	$(MAKE) -C nearn run-vlsim
 	$(MAKE) -C guassian run-vlsim
 	$(MAKE) -C printf run-vlsim
-#$(MAKE) -C psort run-vlsim
+    #$(MAKE) -C psort run-vlsim
 
 clean:
 	$(MAKE) -C vecadd clean

tests/regression/Makefile

@@ -8,7 +8,17 @@ all:
 	$(MAKE) -C diverge
 	$(MAKE) -C fence
 
-run:
+run-simx:
+	$(MAKE) -C basic run-simx
+	$(MAKE) -C demo run-simx
+	$(MAKE) -C dogfood run-simx
+	$(MAKE) -C mstress run-simx
+	$(MAKE) -C io_addr run-simx
+	$(MAKE) -C printf run-simx
+	$(MAKE) -C diverge run-simx
+	$(MAKE) -C fence run-simx
+
+run-vlsim:
 	$(MAKE) -C basic run-vlsim
 	$(MAKE) -C demo run-vlsim
 	$(MAKE) -C dogfood run-vlsim

tests/riscv/Makefile

@@ -1,6 +1,9 @@
 all:
 
-run:
+run-simx:
-	$(MAKE) -C isa run
+	$(MAKE) -C isa run-simx
+
+run-rtlsim:
+	$(MAKE) -C isa run-rtlsim
 
 clean:

tests/riscv/isa/Makefile

@@ -1,8 +1,13 @@
-TESTS := $(wildcard *.hex)
+ALL_TESTS := $(wildcard *.hex)
 
-VTESTS := $(wildcard *-v-*.hex)
+V_TESTS := $(wildcard *-v-*.hex)
 
-TESTS := $(filter-out $(VTESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ud-p-fclass.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ud-p-ldst.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32ud-p-fdiv.hex rv32ud-p-fcmp.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ud-p-fcvt.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32ud-p-fmadd.hex rv32ud-p-fadd.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32ud-p-fmin.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex, $(TESTS))
+EXCLUDED_TESTS := $(V_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ud-p-fclass.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ud-p-ldst.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32ud-p-fdiv.hex rv32ud-p-fcmp.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ud-p-fcvt.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32ud-p-fmadd.hex rv32ud-p-fadd.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32ud-p-fmin.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex
 
-run:
+TESTS := $(filter-out $(EXCLUDED_TESTS), $(ALL_TESTS))
-	cd ../../../hw/simulate/obj_dir && ./VVortex -r $(foreach test,$(TESTS),../../../tests/riscv/isa/$(test))
+
+run-simx:	
+	$(foreach test,$(TESTS), ../../../simX/simX -r -a rv32i -c 1 -i $(test);)
+
+run-rtlsim:
+	$(foreach test,$(TESTS), ../../../hw/simulate/obj_dir/VVortex -r $(test);)

tests/runtime/Makefile

@@ -3,10 +3,15 @@ all:
 	$(MAKE) -C fibonacci
 	$(MAKE) -C simple
 
-run:
+run-simx:
-	$(MAKE) -C hello run
+	$(MAKE) -C hello run-simx
-	$(MAKE) -C fibonacci run
+	$(MAKE) -C fibonacci run-simx
-	$(MAKE) -C simple run
+	$(MAKE) -C simple run-simx
+
+run-rtlsim:
+	$(MAKE) -C hello run-rtlsim
+	$(MAKE) -C fibonacci run-rtlsim
+	$(MAKE) -C simple run-rtlsim
 
 clean:
 	$(MAKE) -C hello clean

tests/runtime/fibonacci/Makefile

@@ -26,11 +26,11 @@ $(PROJECT).hex: $(PROJECT).elf
 $(PROJECT).elf: $(SRCS)
 	$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
 
-run: $(PROJECT).hex
+run-rtlsim: $(PROJECT).hex
 	../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex
 
 run-simx: $(PROJECT).hex
-	../../../simX/simX -a rv32i -i $(PROJECT).hex
+	../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex
 
 .depend: $(SRCS)
 	$(CC) $(CFLAGS) -MM $^ > .depend;

tests/runtime/hello/Makefile

@@ -26,11 +26,11 @@ $(PROJECT).hex: $(PROJECT).elf
 $(PROJECT).elf: $(SRCS)
 	$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
 
-run: $(PROJECT).hex
+run-rtlsim: $(PROJECT).hex
 	../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex
 
 run-simx: $(PROJECT).hex
-	../../../simX/simX -a rv32i -i $(PROJECT).hex
+	../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex
 
 .depend: $(SRCS)
 	$(CC) $(CFLAGS) -MM $^ > .depend;

tests/runtime/simple/Makefile

@@ -26,11 +26,11 @@ $(PROJECT).hex: $(PROJECT).elf
 $(PROJECT).elf: $(SRCS)
 	$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
 
-run: $(PROJECT).hex
+run-rtlsim: $(PROJECT).hex
 	../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex
 
 run-simx: $(PROJECT).hex
-	../../../simX/simX -a rv32i -i $(PROJECT).hex
+	../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex
 
 .depend: $(SRCS)
 	$(CC) $(CFLAGS) -MM $^ > .depend;