From d2ab8d3cc6aa73f191a6e5b6c67a504f0d0cf28a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Carter=20Ren=C3=A9=20Montgomery?= Date: Mon, 5 Oct 2020 14:49:47 -0400 Subject: [PATCH 1/3] Added comments to prep for cache presentation --- hw/rtl/cache/VX_bank.v | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 21125640..05f58ebe 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -263,7 +263,8 @@ module VX_bank #( `DEBUG_BEGIN wire going_to_write_st1; `DEBUG_END - + + //determines if the if it is time to pop a req from the queues wire mrvq_pop_unqual = mrvq_valid_st0; wire dfpq_pop_unqual = !mrvq_pop_unqual && !dfpq_empty; wire reqq_pop_unqual = !mrvq_stop && !mrvq_pop_unqual && !dfpq_pop_unqual && !reqq_empty && reqq_req_st0 && !is_fill_st1 && !is_fill_st1; @@ -297,15 +298,19 @@ module VX_bank #( wire snp_invalidate_st1; wire is_mrvq_st1; - assign qual_is_fill_st0 = dfpq_pop_unqual; + //why is the signal prefixed with qual? + assign qual_is_fill_st0 = dfpq_pop_unqual; //dram is filling a request - assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop; + assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop; //valid if something is being popped + //decides which request to deal with. Priority: 1) DRAM fill, 2) Miss reserve 3) Core req 4) Snp req assign qual_addr_st0 = dfpq_pop_unqual ? dfpq_addr_st0 : mrvq_pop_unqual ? mrvq_addr_st0 : reqq_pop_unqual ? reqq_req_addr_st0[`LINE_SELECT_ADDR_RNG] : snrq_pop_unqual ? snrq_addr_st0 : 0; + + //Word select does ? Does this just pick a specific word from the line instead of the whole line? if (`WORD_SELECT_WIDTH != 0) begin assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`WORD_SELECT_WIDTH-1:0] : mrvq_pop_unqual ? mrvq_wsel_st0 : @@ -315,8 +320,10 @@ module VX_bank #( assign qual_wsel_st0 = 0; end + //if you are filling from dram then that is the write data? What about core? What is 57? assign qual_writedata_st0 = dfpq_pop_unqual ? dfpq_filldata_st0 : 57; + // assign qual_inst_meta_st0 = mrvq_pop_unqual ? {`REQ_TAG_WIDTH'(mrvq_tag_st0) , mrvq_rw_st0, mrvq_byteen_st0, mrvq_tid_st0} : reqq_pop_unqual ? {`REQ_TAG_WIDTH'(reqq_req_tag_st0), reqq_req_rw_st0, reqq_req_byteen_st0, reqq_req_tid_st0} : snrq_pop_unqual ? {`REQ_TAG_WIDTH'(snrq_tag_st0), 1'b0, WORD_SIZE'(0), `REQS_BITS'(0)} : @@ -327,6 +334,7 @@ module VX_bank #( (reqq_pop_unqual && reqq_req_rw_st0) ? 1 : 0; + //snp signals check to see if the miss reserve as a snp in it first. assign qual_is_snp_st0 = mrvq_pop_unqual ? mrvq_is_snp_st0 : snrq_pop_unqual ? 1 : 0; From 1f4af4777cc512713241d11239d56420ef581e4a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Carter=20Ren=C3=A9=20Montgomery?= Date: Tue, 6 Oct 2020 14:35:46 -0400 Subject: [PATCH 2/3] Comments --- hw/rtl/cache/VX_bank.v | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 05f58ebe..f4fc7df5 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -265,6 +265,7 @@ module VX_bank #( `DEBUG_END //determines if the if it is time to pop a req from the queues + //unqual - the req does NOT qualify for execution in the bank. wire mrvq_pop_unqual = mrvq_valid_st0; wire dfpq_pop_unqual = !mrvq_pop_unqual && !dfpq_empty; wire reqq_pop_unqual = !mrvq_stop && !mrvq_pop_unqual && !dfpq_pop_unqual && !reqq_empty && reqq_req_st0 && !is_fill_st1 && !is_fill_st1; @@ -274,7 +275,8 @@ module VX_bank #( assign dfpq_pop = dfpq_pop_unqual && !stall_bank_pipe; assign reqq_pop = reqq_pop_unqual && !stall_bank_pipe; assign snrq_pop = snrq_pop_unqual && !stall_bank_pipe; - + + //signals to progress to the next stage wire qual_is_fill_st0; wire qual_valid_st0; wire [`LINE_ADDR_WIDTH-1:0] qual_addr_st0; @@ -287,7 +289,8 @@ module VX_bank #( wire qual_going_to_write_st0; wire qual_is_snp_st0; wire qual_snp_invalidate_st0; - + + //signals to be *used* in the next stage wire valid_st1; wire [`LINE_ADDR_WIDTH-1:0] addr_st1; wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st1; @@ -298,7 +301,7 @@ module VX_bank #( wire snp_invalidate_st1; wire is_mrvq_st1; - //why is the signal prefixed with qual? + //Determine which req will progress to the next stage assign qual_is_fill_st0 = dfpq_pop_unqual; //dram is filling a request assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop; //valid if something is being popped @@ -323,12 +326,13 @@ module VX_bank #( //if you are filling from dram then that is the write data? What about core? What is 57? assign qual_writedata_st0 = dfpq_pop_unqual ? dfpq_filldata_st0 : 57; - // + //note that this is stored even if a DRAM fill is processed assign qual_inst_meta_st0 = mrvq_pop_unqual ? {`REQ_TAG_WIDTH'(mrvq_tag_st0) , mrvq_rw_st0, mrvq_byteen_st0, mrvq_tid_st0} : reqq_pop_unqual ? {`REQ_TAG_WIDTH'(reqq_req_tag_st0), reqq_req_rw_st0, reqq_req_byteen_st0, reqq_req_tid_st0} : snrq_pop_unqual ? {`REQ_TAG_WIDTH'(snrq_tag_st0), 1'b0, WORD_SIZE'(0), `REQS_BITS'(0)} : 0; - + + assign qual_going_to_write_st0 = dfpq_pop_unqual ? 1 : (mrvq_pop_unqual && mrvq_rw_st0) ? 1 : (reqq_pop_unqual && reqq_req_rw_st0) ? 1 : @@ -338,15 +342,16 @@ module VX_bank #( assign qual_is_snp_st0 = mrvq_pop_unqual ? mrvq_is_snp_st0 : snrq_pop_unqual ? 1 : 0; - + //if we are popping from the miss reserve then assign to the mrvq invalidate. If not and popping from the snoop queue use the snoop invalidate. Else this is 0 assign qual_snp_invalidate_st0 = mrvq_pop_unqual ? mrvq_snp_invalidate_st0 : snrq_pop_unqual ? snrq_invalidate_st0 : 0; - + //choose which word of the lien is being written to assign qual_writeword_st0 = mrvq_pop_unqual ? mrvq_writeword_st0 : reqq_pop_unqual ? reqq_req_writeword_st0 : 0; + assign qual_is_mrvq_st0 = mrvq_pop_unqual; `ifdef DBG_CORE_REQ_INFO From a83048b3bd952447399e0343a7f2c41bf98f6d97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Carter=20Ren=C3=A9=20Montgomery?= Date: Tue, 6 Oct 2020 14:50:56 -0400 Subject: [PATCH 3/3] Comments --- hw/rtl/cache/VX_tag_data_store.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/rtl/cache/VX_tag_data_store.v b/hw/rtl/cache/VX_tag_data_store.v index e0f356cc..e33fc33f 100644 --- a/hw/rtl/cache/VX_tag_data_store.v +++ b/hw/rtl/cache/VX_tag_data_store.v @@ -6,7 +6,7 @@ module VX_tag_data_store #( // Size of line inside a bank in bytes parameter BANK_LINE_SIZE = 0, // Number of banks {1, 2, 4, 8,...} - parameter NUM_BANKS = 0, + parameter NUM_BANKS = 0, //unused parameter? // Size of a word in bytes parameter WORD_SIZE = 0 ) ( @@ -80,4 +80,4 @@ module VX_tag_data_store #( end end -endmodule \ No newline at end of file +endmodule