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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 09:24:04 -04:00
parent 3139d37610
commit e9dfa828fe
33 changed files with 998 additions and 1022 deletions
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30
hw/rtl/VX_gpr_wrapper.v
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@@ -3,9 +3,9 @@
module VX_gpr_wrapper (
input wire clk,
input wire reset,
VX_gpr_read_if vx_gpr_read,
VX_wb_if vx_writeback_if,
VX_gpr_jal_if vx_gpr_jal,
VX_gpr_read_if gpr_read_if,
VX_wb_if writeback_if,
VX_gpr_jal_if gpr_jal_if,
output wire[`NUM_THREADS-1:0][31:0] out_a_reg_data,
output wire[`NUM_THREADS-1:0][31:0] out_b_reg_data
@@ -19,13 +19,13 @@ module VX_gpr_wrapper (
genvar index;
generate
for (index = 0; index < `NUM_THREADS; index = index + 1) begin : jal_data_assign
assign jal_data[index] = vx_gpr_jal.curr_PC;
assign jal_data[index] = gpr_jal_if.curr_PC;
end
endgenerate
`ifndef ASIC
assign out_a_reg_data = (vx_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[vx_gpr_read.warp_num]));
assign out_b_reg_data = (temp_b_reg_data[vx_gpr_read.warp_num]);
assign out_a_reg_data = (gpr_jal_if.is_jal ? jal_data : (temp_a_reg_data[gpr_read_if.warp_num]));
assign out_b_reg_data = (temp_b_reg_data[gpr_read_if.warp_num]);
`else
wire zer = 0;
@@ -38,31 +38,29 @@ module VX_gpr_wrapper (
.reset(reset),
.stall(zer),
.flush(zer),
.in (vx_gpr_read.warp_num),
.in (gpr_read_if.warp_num),
.out (old_warp_num)
);
assign out_a_reg_data = (vx_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[old_warp_num]));
assign out_a_reg_data = (gpr_jal_if.is_jal ? jal_data : (temp_a_reg_data[old_warp_num]));
assign out_b_reg_data = (temp_b_reg_data[old_warp_num]);
`endif
genvar warp_index;
generate
for (warp_index = 0; warp_index < `NUM_WARPS; warp_index = warp_index + 1) begin : warp_gprs
wire valid_write_request = warp_index == vx_writeback_if.wb_warp_num;
VX_gpr vx_gpr(
wire valid_write_request = warp_index == writeback_if.wb_warp_num;
VX_gpr gpr(
.clk (clk),
.reset (reset),
.valid_write_request(valid_write_request),
.vx_gpr_read (vx_gpr_read),
.vx_writeback_if (vx_writeback_if),
.gpr_read_if (gpr_read_if),
.writeback_if (writeback_if),
.out_a_reg_data (temp_a_reg_data[warp_index]),
.out_b_reg_data (temp_b_reg_data[warp_index])
);
);
end
endgenerate