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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 09:24:04 -04:00
parent 3139d37610
commit e9dfa828fe
33 changed files with 998 additions and 1022 deletions
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112
hw/rtl/VX_inst_multiplex.v
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@@ -2,23 +2,23 @@
module VX_inst_multiplex (
// Inputs
VX_frE_to_bckE_req_if vx_bckE_req,
VX_gpr_data_if vx_gpr_data,
VX_frE_to_bckE_req_if bckE_req_if,
VX_gpr_data_if gpr_data_if,
// Outputs
VX_exec_unit_req_if vx_exec_unit_req,
VX_lsu_req_if vx_lsu_req,
VX_gpu_inst_req_if vx_gpu_inst_req,
VX_csr_req_if vx_csr_req
VX_exec_unit_req_if exec_unit_req_if,
VX_lsu_req_if lsu_req_if,
VX_gpu_inst_req_if gpu_inst_req_if,
VX_csr_req_if csr_req_if
);
wire[`NUM_THREADS-1:0] is_mem_mask;
wire[`NUM_THREADS-1:0] is_gpu_mask;
wire[`NUM_THREADS-1:0] is_csr_mask;
wire is_mem = (vx_bckE_req.mem_write != `NO_MEM_WRITE) || (vx_bckE_req.mem_read != `NO_MEM_READ);
wire is_gpu = (vx_bckE_req.is_wspawn || vx_bckE_req.is_tmc || vx_bckE_req.is_barrier || vx_bckE_req.is_split);
wire is_csr = vx_bckE_req.is_csr;
wire is_mem = (bckE_req_if.mem_write != `NO_MEM_WRITE) || (bckE_req_if.mem_read != `NO_MEM_READ);
wire is_gpu = (bckE_req_if.is_wspawn || bckE_req_if.is_tmc || bckE_req_if.is_barrier || bckE_req_if.is_split);
wire is_csr = bckE_req_if.is_csr;
// wire is_gpu = 0;
genvar currT;
@@ -31,64 +31,64 @@ module VX_inst_multiplex (
endgenerate
// LSU Unit
assign vx_lsu_req.valid = vx_bckE_req.valid & is_mem_mask;
assign vx_lsu_req.warp_num = vx_bckE_req.warp_num;
assign vx_lsu_req.base_address = vx_gpr_data.a_reg_data;
assign vx_lsu_req.store_data = vx_gpr_data.b_reg_data;
assign lsu_req_if.valid = bckE_req_if.valid & is_mem_mask;
assign lsu_req_if.warp_num = bckE_req_if.warp_num;
assign lsu_req_if.base_address = gpr_data_if.a_reg_data;
assign lsu_req_if.store_data = gpr_data_if.b_reg_data;
assign vx_lsu_req.offset = vx_bckE_req.itype_immed;
assign lsu_req_if.offset = bckE_req_if.itype_immed;
assign vx_lsu_req.mem_read = vx_bckE_req.mem_read;
assign vx_lsu_req.mem_write = vx_bckE_req.mem_write;
assign vx_lsu_req.rd = vx_bckE_req.rd;
assign vx_lsu_req.wb = vx_bckE_req.wb;
assign vx_lsu_req.lsu_pc = vx_bckE_req.curr_PC;
assign lsu_req_if.mem_read = bckE_req_if.mem_read;
assign lsu_req_if.mem_write = bckE_req_if.mem_write;
assign lsu_req_if.rd = bckE_req_if.rd;
assign lsu_req_if.wb = bckE_req_if.wb;
assign lsu_req_if.lsu_pc = bckE_req_if.curr_PC;
// Execute Unit
assign vx_exec_unit_req.valid = vx_bckE_req.valid & (~is_mem_mask & ~is_gpu_mask & ~is_csr_mask);
assign vx_exec_unit_req.warp_num = vx_bckE_req.warp_num;
assign vx_exec_unit_req.curr_PC = vx_bckE_req.curr_PC;
assign vx_exec_unit_req.PC_next = vx_bckE_req.PC_next;
assign vx_exec_unit_req.rd = vx_bckE_req.rd;
assign vx_exec_unit_req.wb = vx_bckE_req.wb;
assign vx_exec_unit_req.a_reg_data = vx_gpr_data.a_reg_data;
assign vx_exec_unit_req.b_reg_data = vx_gpr_data.b_reg_data;
assign vx_exec_unit_req.alu_op = vx_bckE_req.alu_op;
assign vx_exec_unit_req.rs1 = vx_bckE_req.rs1;
assign vx_exec_unit_req.rs2 = vx_bckE_req.rs2;
assign vx_exec_unit_req.rs2_src = vx_bckE_req.rs2_src;
assign vx_exec_unit_req.itype_immed = vx_bckE_req.itype_immed;
assign vx_exec_unit_req.upper_immed = vx_bckE_req.upper_immed;
assign vx_exec_unit_req.branch_type = vx_bckE_req.branch_type;
assign vx_exec_unit_req.jalQual = vx_bckE_req.jalQual;
assign vx_exec_unit_req.jal = vx_bckE_req.jal;
assign vx_exec_unit_req.jal_offset = vx_bckE_req.jal_offset;
assign vx_exec_unit_req.ebreak = vx_bckE_req.ebreak;
assign exec_unit_req_if.valid = bckE_req_if.valid & (~is_mem_mask & ~is_gpu_mask & ~is_csr_mask);
assign exec_unit_req_if.warp_num = bckE_req_if.warp_num;
assign exec_unit_req_if.curr_PC = bckE_req_if.curr_PC;
assign exec_unit_req_if.PC_next = bckE_req_if.PC_next;
assign exec_unit_req_if.rd = bckE_req_if.rd;
assign exec_unit_req_if.wb = bckE_req_if.wb;
assign exec_unit_req_if.a_reg_data = gpr_data_if.a_reg_data;
assign exec_unit_req_if.b_reg_data = gpr_data_if.b_reg_data;
assign exec_unit_req_if.alu_op = bckE_req_if.alu_op;
assign exec_unit_req_if.rs1 = bckE_req_if.rs1;
assign exec_unit_req_if.rs2 = bckE_req_if.rs2;
assign exec_unit_req_if.rs2_src = bckE_req_if.rs2_src;
assign exec_unit_req_if.itype_immed = bckE_req_if.itype_immed;
assign exec_unit_req_if.upper_immed = bckE_req_if.upper_immed;
assign exec_unit_req_if.branch_type = bckE_req_if.branch_type;
assign exec_unit_req_if.jalQual = bckE_req_if.jalQual;
assign exec_unit_req_if.jal = bckE_req_if.jal;
assign exec_unit_req_if.jal_offset = bckE_req_if.jal_offset;
assign exec_unit_req_if.ebreak = bckE_req_if.ebreak;
// GPR Req
assign vx_gpu_inst_req.valid = vx_bckE_req.valid & is_gpu_mask;
assign vx_gpu_inst_req.warp_num = vx_bckE_req.warp_num;
assign vx_gpu_inst_req.is_wspawn = vx_bckE_req.is_wspawn;
assign vx_gpu_inst_req.is_tmc = vx_bckE_req.is_tmc;
assign vx_gpu_inst_req.is_split = vx_bckE_req.is_split;
assign vx_gpu_inst_req.is_barrier = vx_bckE_req.is_barrier;
assign vx_gpu_inst_req.a_reg_data = vx_gpr_data.a_reg_data;
assign vx_gpu_inst_req.rd2 = vx_gpr_data.b_reg_data[0];
assign vx_gpu_inst_req.pc_next = vx_bckE_req.PC_next;
assign gpu_inst_req_if.valid = bckE_req_if.valid & is_gpu_mask;
assign gpu_inst_req_if.warp_num = bckE_req_if.warp_num;
assign gpu_inst_req_if.is_wspawn = bckE_req_if.is_wspawn;
assign gpu_inst_req_if.is_tmc = bckE_req_if.is_tmc;
assign gpu_inst_req_if.is_split = bckE_req_if.is_split;
assign gpu_inst_req_if.is_barrier = bckE_req_if.is_barrier;
assign gpu_inst_req_if.a_reg_data = gpr_data_if.a_reg_data;
assign gpu_inst_req_if.rd2 = gpr_data_if.b_reg_data[0];
assign gpu_inst_req_if.pc_next = bckE_req_if.PC_next;
// CSR Req
assign vx_csr_req.valid = vx_bckE_req.valid & is_csr_mask;
assign vx_csr_req.warp_num = vx_bckE_req.warp_num;
assign vx_csr_req.rd = vx_bckE_req.rd;
assign vx_csr_req.wb = vx_bckE_req.wb;
assign vx_csr_req.alu_op = vx_bckE_req.alu_op;
assign vx_csr_req.is_csr = vx_bckE_req.is_csr;
assign vx_csr_req.csr_address = vx_bckE_req.csr_address;
assign vx_csr_req.csr_immed = vx_bckE_req.csr_immed;
assign vx_csr_req.csr_mask = vx_bckE_req.csr_mask;
assign csr_req_if.valid = bckE_req_if.valid & is_csr_mask;
assign csr_req_if.warp_num = bckE_req_if.warp_num;
assign csr_req_if.rd = bckE_req_if.rd;
assign csr_req_if.wb = bckE_req_if.wb;
assign csr_req_if.alu_op = bckE_req_if.alu_op;
assign csr_req_if.is_csr = bckE_req_if.is_csr;
assign csr_req_if.csr_address = bckE_req_if.csr_address;
assign csr_req_if.csr_immed = bckE_req_if.csr_immed;
assign csr_req_if.csr_mask = bckE_req_if.csr_mask;
endmodule