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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 09:24:04 -04:00
parent 3139d37610
commit e9dfa828fe
33 changed files with 998 additions and 1022 deletions
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58
hw/rtl/VX_lsu.v
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@@ -1,23 +1,23 @@
`include "VX_define.vh"
module VX_lsu (
input wire clk,
input wire reset,
input wire no_slot_mem,
VX_lsu_req_if vx_lsu_req,
input wire clk,
input wire reset,
input wire no_slot_mem,
VX_lsu_req_if lsu_req_if,
// Write back to GPR
VX_inst_mem_wb_if vx_mem_wb,
VX_inst_mem_wb_if mem_wb_if,
VX_gpu_dcache_rsp_if vx_dcache_rsp,
VX_gpu_dcache_req_if vx_dcache_req,
output wire out_delay
VX_gpu_dcache_rsp_if dcache_rsp_if,
VX_gpu_dcache_req_if dcache_req_if,
output wire out_delay
);
// Generate Addresses
wire[`NUM_THREADS-1:0][31:0] address;
VX_lsu_addr_gen VX_lsu_addr_gen (
.base_address (vx_lsu_req.base_address),
.offset (vx_lsu_req.offset),
.base_address (lsu_req_if.base_address),
.offset (lsu_req_if.offset),
.address (address)
);
@@ -40,33 +40,33 @@ module VX_lsu (
.reset(reset),
.stall(out_delay),
.flush(zero),
.in ({address , vx_lsu_req.store_data, vx_lsu_req.valid, vx_lsu_req.mem_read, vx_lsu_req.mem_write, vx_lsu_req.rd, vx_lsu_req.warp_num, vx_lsu_req.wb, vx_lsu_req.lsu_pc}),
.in ({address , lsu_req_if.store_data, lsu_req_if.valid, lsu_req_if.mem_read, lsu_req_if.mem_write, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.lsu_pc}),
.out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc })
);
// Core Request
assign vx_dcache_req.core_req_valid = use_valid;
assign vx_dcache_req.core_req_addr = use_address;
assign vx_dcache_req.core_req_writedata = use_store_data;
assign vx_dcache_req.core_req_mem_read = {`NUM_THREADS{use_mem_read}};
assign vx_dcache_req.core_req_mem_write = {`NUM_THREADS{use_mem_write}};
assign vx_dcache_req.core_req_rd = use_rd;
assign vx_dcache_req.core_req_wb = {`NUM_THREADS{use_wb}};
assign vx_dcache_req.core_req_warp_num = use_warp_num;
assign vx_dcache_req.core_req_pc = use_pc;
assign dcache_req_if.core_req_valid = use_valid;
assign dcache_req_if.core_req_addr = use_address;
assign dcache_req_if.core_req_writedata = use_store_data;
assign dcache_req_if.core_req_mem_read = {`NUM_THREADS{use_mem_read}};
assign dcache_req_if.core_req_mem_write = {`NUM_THREADS{use_mem_write}};
assign dcache_req_if.core_req_rd = use_rd;
assign dcache_req_if.core_req_wb = {`NUM_THREADS{use_wb}};
assign dcache_req_if.core_req_warp_num = use_warp_num;
assign dcache_req_if.core_req_pc = use_pc;
// Core can't accept response
assign vx_dcache_req.core_no_wb_slot = no_slot_mem;
assign dcache_req_if.core_no_wb_slot = no_slot_mem;
// Cache can't accept request
assign out_delay = vx_dcache_rsp.delay_req;
assign out_delay = dcache_rsp_if.delay_req;
// Core Response
assign vx_mem_wb.rd = vx_dcache_rsp.core_wb_req_rd;
assign vx_mem_wb.wb = vx_dcache_rsp.core_wb_req_wb;
assign vx_mem_wb.wb_valid = vx_dcache_rsp.core_wb_valid;
assign vx_mem_wb.wb_warp_num = vx_dcache_rsp.core_wb_warp_num;
assign vx_mem_wb.loaded_data = vx_dcache_rsp.core_wb_readdata;
assign mem_wb_if.rd = dcache_rsp_if.core_wb_req_rd;
assign mem_wb_if.wb = dcache_rsp_if.core_wb_req_wb;
assign mem_wb_if.wb_valid = dcache_rsp_if.core_wb_valid;
assign mem_wb_if.wb_warp_num = dcache_rsp_if.core_wb_warp_num;
assign mem_wb_if.loaded_data = dcache_rsp_if.core_wb_readdata;
wire[(`LOG2UP(`NUM_THREADS))-1:0] use_pc_index;
@@ -75,12 +75,12 @@ module VX_lsu (
`DEBUG_END
VX_generic_priority_encoder #(.N(`NUM_THREADS)) pick_first_pc(
.valids(vx_dcache_rsp.core_wb_valid),
.valids(dcache_rsp_if.core_wb_valid),
.index (use_pc_index),
.found (found)
);
assign vx_mem_wb.mem_wb_pc = vx_dcache_rsp.core_wb_pc[use_pc_index];
assign mem_wb_if.mem_wb_pc = dcache_rsp_if.core_wb_pc[use_pc_index];
endmodule // Memory