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Icache/Dcache finally done + configurability tested:

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This commit is contained in:
felsabbagh3
2019-11-09 00:03:15 -05:00
parent 8b81989bfd
commit ea7bd485ca
8 changed files with 517 additions and 349 deletions
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2
rtl/VX_define.v
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@@ -136,7 +136,7 @@
`define ICACHE_WAYS 2
`endif
//Bytes
`define ICACHE_BLOCK 8
`define ICACHE_BLOCK 16
`define ICACHE_BANKS 1
`define ICACHE_LOG_NUM_BANKS `CLOG2(`ICACHE_BANKS)

15
rtl/cache/VX_Cache_Bank.v vendored
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@@ -56,8 +56,7 @@ module VX_Cache_Bank
eviction_addr, // What's the eviction tag
data_evicted,
evicted_way,
way_use
evicted_way
);
// localparam NUMBER_BANKS = `CACHE_BANKS;
@@ -69,6 +68,8 @@ module VX_Cache_Bank
localparam SEND_MEM_REQ = 1; // Write back this block into memory
localparam RECIV_MEM_RSP = 2;
localparam BLOCK_NUM_BITS = `CLOG2(CACHE_BLOCK);
// Inputs
input wire rst;
input wire clk;
@@ -94,7 +95,6 @@ module VX_Cache_Bank
input wire[CACHE_WAY_INDEX-1:0] evicted_way;
output wire[CACHE_WAY_INDEX-1:0] way_use;
// Outputs
// Normal shit
@@ -122,7 +122,6 @@ module VX_Cache_Bank
wire[CACHE_WAY_INDEX-1:0] update_way;
wire[CACHE_WAY_INDEX-1:0] way_to_update;
assign miss = (tag_use != o_tag) && valid_use && valid_in;
@@ -137,8 +136,7 @@ module VX_Cache_Bank
assign write_from_mem = (state == RECIV_MEM_RSP) && valid_in; // TODO
assign hit = (access && (tag_use == o_tag) && valid_use);
//assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data
assign eviction_addr = {eviction_tag, actual_index, 7'b0}; // Fix with actual data
assign update_way = hit ? way_use : 0;
assign eviction_addr = {eviction_tag, actual_index, {(BLOCK_NUM_BITS){1'b0}}}; // Fix with actual data
@@ -215,7 +213,7 @@ module VX_Cache_Bank
// assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0;
assign data_write[g] = write_from_mem ? fetched_writedata[g] : use_write_data;
assign way_to_update = write_from_mem ? evicted_way : update_way;
assign way_to_update = evicted_way;
end
@@ -243,8 +241,7 @@ module VX_Cache_Bank
.tag_use (tag_use),
.data_use (data_use),
.valid_use (valid_use),
.dirty_use (dirty_use),
.way (way_use)
.dirty_use (dirty_use)
);

77
rtl/cache/VX_cache_data_per_index.v vendored
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@@ -32,8 +32,7 @@ module VX_cache_data_per_index
output wire[TAG_SIZE_END:TAG_SIZE_START] tag_use,
output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use,
output wire dirty_use,
output wire[CACHE_WAY_INDEX-1:0] way
output wire dirty_use
);
//localparam NUMBER_BANKS = CACHE_BANKS;
@@ -46,7 +45,7 @@ module VX_cache_data_per_index
wire [CACHE_WAYS-1:0] valid_use_per_way;
wire [CACHE_WAYS-1:0] dirty_use_per_way;
wire [CACHE_WAYS-1:0] hit_per_way;
reg [CACHE_WAY_INDEX-1:0] eviction_way_index;
// reg [CACHE_WAY_INDEX-1:0] eviction_way_index;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way;
wire [CACHE_WAYS-1:0] write_from_mem_per_way;
@@ -84,26 +83,44 @@ module VX_cache_data_per_index
wire hit = |hit_per_way;
wire miss = ~hit;
wire update = |we && !miss;
wire valid = &valid_use_per_way;
// wire hit = |hit_per_way;
// wire miss = ~hit;
// wire update = |we && !miss;
// wire valid = &valid_use_per_way;
assign way = hit ? way_index : (valid ? eviction_way_index : (invalid_found ? invalid_index : 0));
assign tag_use = hit ? tag_use_per_way[way_index] : (valid ? tag_use_per_way[eviction_way_index] : (invalid_found ? tag_use_per_way[invalid_index] : 0));
assign data_use = hit ? data_use_per_way[way_index] : (valid ? data_use_per_way[eviction_way_index] : (invalid_found ? data_use_per_way[invalid_index] : 0));
assign valid_use = hit ? valid_use_per_way[way_index] : (valid ? valid_use_per_way[eviction_way_index] : (invalid_found ? valid_use_per_way[invalid_index] : 0));
assign dirty_use = hit ? dirty_use_per_way[way_index] : (valid ? dirty_use_per_way[eviction_way_index] : (invalid_found ? dirty_use_per_way[invalid_index] : 0));
wire[CACHE_WAY_INDEX-1:0] way_use_Qual;
assign way_use_Qual = (state != CACHE_IDLE) ? way_to_update : way_index;
assign tag_use = tag_use_per_way[way_use_Qual];
assign data_use = data_use_per_way[way_use_Qual];
assign valid_use = valid_use_per_way[way_use_Qual];
assign dirty_use = dirty_use_per_way[way_use_Qual];
// assign tag_use = hit ? tag_use_per_way[way_index] : (valid ? tag_use_per_way[eviction_way_index] : (invalid_found ? tag_use_per_way[invalid_index] : 0));
// assign data_use = hit ? data_use_per_way[way_index] : (valid ? data_use_per_way[eviction_way_index] : (invalid_found ? data_use_per_way[invalid_index] : 0));
// assign valid_use = hit ? valid_use_per_way[way_index] : (valid ? valid_use_per_way[eviction_way_index] : (invalid_found ? valid_use_per_way[invalid_index] : 0));
// assign dirty_use = hit ? dirty_use_per_way[way_index] : (valid ? dirty_use_per_way[eviction_way_index] : (invalid_found ? dirty_use_per_way[invalid_index] : 0));
genvar ways;
for(ways=0; ways < CACHE_WAYS; ways = ways + 1) begin : each_way
assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? (we) : 0) : 0;
assign data_write_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? data_write : 0) : 0;
assign write_from_mem_per_way[ways] = (evict == 1'b1) ? ((ways == way_to_update) ? 1 : 0) : 0;
assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
assign write_from_mem_per_way[ways] = evict && (ways == way_use_Qual);
assign we_per_way[ways] = (ways == way_use_Qual) ? (we) : 0;
assign data_write_per_way[ways] = data_write;
// assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
// assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_use_Qual) ? (we) : 0) : 0;
// assign data_write_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_use_Qual) ? data_write : 0) : 0;
// assign write_from_mem_per_way[ways] = (evict == 1'b1) ? ((ways == way_use_Qual) ? 1 : 0) : 0;
VX_cache_data #(
.NUM_IND (NUM_IND),
@@ -128,19 +145,19 @@ module VX_cache_data_per_index
);
end
always @(posedge clk or posedge rst) begin
if (rst) begin
eviction_way_index <= 0;
end else begin
// if((miss && dirty_use && valid_use && !evict && valid_in)) begin // can be either evict or invalid cache entries
if((state == SEND_MEM_REQ)) begin // can be either evict or invalid cache entries
if((eviction_way_index+1) == CACHE_WAYS) begin
eviction_way_index <= 0;
end else begin
eviction_way_index <= (eviction_way_index + 1);
end
end
end
end
// always @(posedge clk or posedge rst) begin
// if (rst) begin
// eviction_way_index <= 0;
// end else begin
// // if((miss && dirty_use && valid_use && !evict && valid_in)) begin // can be either evict or invalid cache entries
// if((state == SEND_MEM_REQ)) begin // can be either evict or invalid cache entries
// if((eviction_way_index+1) == CACHE_WAYS) begin
// eviction_way_index <= 0;
// end else begin
// eviction_way_index <= (eviction_way_index + 1);
// end
// end
// end
// end
endmodule

51
rtl/cache/VX_d_cache.v vendored
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@@ -103,6 +103,8 @@ module VX_d_cache
assign o_p_readdata = new_final_data_read_Qual;
reg[CACHE_WAY_INDEX-1:0] global_way_to_evict;
wire[CACHE_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank
wire[CACHE_BANKS - 1 : 0][LOG_NUM_REQ-1:0] index_per_bank; // Index of thread each bank will try to service
@@ -116,9 +118,9 @@ module VX_d_cache
reg[CACHE_BANKS-1:0] eviction_wb_old;
wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_new;
reg [CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_old;
wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] way_used;
// wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_new;
// reg [CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_old;
// wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] way_used;
// Internal State
reg [3:0] state;
@@ -133,7 +135,7 @@ module VX_d_cache
reg[CACHE_BANKS - 1 : 0][31:0] eviction_addr_per_bank;
reg[31:0] miss_addr;
reg[31:0] evict_addr;
// reg[31:0] evict_addr;
wire curr_processor_request_valid = (|i_p_valid);
@@ -240,6 +242,9 @@ module VX_d_cache
// Handle if there is more than one miss
assign new_stored_valid = use_valid & (~threads_serviced_Qual);
wire update_global_way_to_evict = ((state == RECIV_MEM_RSP) && (new_state == CACHE_IDLE) && (CACHE_WAYS)) && (CACHE_WAYS > 1);
///////////////////////////////////////////////////////////////////////
genvar cur_t;
integer init_b;
@@ -251,28 +256,37 @@ module VX_d_cache
stored_valid <= 0;
// eviction_addr_per_bank <= 0;
miss_addr <= 0;
evict_addr <= 0;
// evict_addr <= 0;
// threads_serviced_Qual = 0;
// for (init_b = 0; init_b < NUMBER_BANKS; init_b=init_b+1)
// begin
// debug_hit_per_bank_mask[init_b] <= 0;
// end
evicted_way_old <= 0;
eviction_wb_old <= 0;
// evicted_way_old <= 0;
// eviction_wb_old <= 0;
global_way_to_evict <= 0;
end else begin
global_way_to_evict <= (update_global_way_to_evict) ? (global_way_to_evict+1) : global_way_to_evict;
state <= new_state;
stored_valid <= new_stored_valid;
if (miss_found) begin
miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]];
evict_addr <= eviction_addr_per_bank[miss_bank_index];
if (state == CACHE_IDLE) begin
if (miss_found) begin
miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]];
// evict_addr <= eviction_addr_per_bank[miss_bank_index];
end else begin
miss_addr <= 0;
// evict_addr <= 0;
end
end
final_data_read <= new_final_data_read_Qual;
evicted_way_old <= evicted_way_new;
eviction_wb_old <= eviction_wb;
// evicted_way_old <= evicted_way_new;
// eviction_wb_old <= eviction_wb;
end
end
@@ -281,13 +295,13 @@ module VX_d_cache
generate
for (bank_id = 0; bank_id < CACHE_BANKS; bank_id = bank_id + 1)
begin
wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? evict_addr :
wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? miss_addr :
(state == RECIV_MEM_RSP) ? miss_addr :
i_p_addr[send_index_to_bank[bank_id]];
assign evicted_way_new[bank_id] = (state == SEND_MEM_REQ) ? way_used[bank_id] :
(state == RECIV_MEM_RSP) ? evicted_way_old[bank_id] :
0;
// assign evicted_way_new[bank_id] = (state == SEND_MEM_REQ) ? way_used[bank_id] :
// (state == RECIV_MEM_RSP) ? evicted_way_old[bank_id] :
// 0;
wire[1:0] byte_select = bank_addr[1:0];
wire[OFFSET_SIZE_END:OFFSET_SIZE_START] cache_offset = bank_addr[ADDR_OFFSET_END:ADDR_OFFSET_START];
@@ -344,8 +358,7 @@ module VX_d_cache
.data_evicted (o_m_writedata[bank_id]),
.eviction_wb (eviction_wb[bank_id]), // Something needs to be written back
.fetched_writedata(i_m_readdata[bank_id]), // Data From memory
.evicted_way (evicted_way_new[bank_id]),
.way_use (way_used[bank_id])
.evicted_way (global_way_to_evict)
);
end
@@ -354,7 +367,7 @@ module VX_d_cache
// Mem Rsp
// Req to mem:
assign o_m_evict_addr = evict_addr & MEM_ADDR_REQ_MASK;
assign o_m_evict_addr = (eviction_addr_per_bank[0]) & MEM_ADDR_REQ_MASK; // Could be anything because tag+index are same
assign o_m_read_addr = miss_addr & MEM_ADDR_REQ_MASK;
assign o_m_valid = (state == SEND_MEM_REQ);
assign o_m_read_or_write = (state == SEND_MEM_REQ) && (|eviction_wb);