From eb307edd9c68c327b19663a349720dac0f2be9f7 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 23 Nov 2020 17:34:06 -0800 Subject: [PATCH] minor update --- .travis.yml | 8 +-- hw/rtl/Vortex.v | 4 +- hw/rtl/libs/VX_dp_ram.v | 110 ++-------------------------------------- 3 files changed, 9 insertions(+), 113 deletions(-) diff --git a/.travis.yml b/.travis.yml index 98b7d6ad..46533b0d 100644 --- a/.travis.yml +++ b/.travis.yml @@ -32,10 +32,10 @@ script: - travis_wait 45 ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 - travis_wait 45 ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=2 - travis_wait 45 ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=4 - - travis_wait 45 ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=2 --l2cache - - travis_wait 45 ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=4 --l2cache - - travis_wait 45 ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=2 --l2cache --clusters=2 - - travis_wait 45 ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=2 --l2cache --clusters=4 + - travis_wait 45 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache + - travis_wait 45 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=4 --l2cache + - travis_wait 45 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --clusters=2 + - travis_wait 45 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --clusters=4 after_success: # Gather code coverage diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 319c89f5..28a75195 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -489,9 +489,9 @@ module Vortex ( always @(posedge clk) begin if (dram_req_valid && dram_req_ready) begin if (dram_req_rw) - $display("%t: DRAM Wr Req: rw=%b addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen, dram_req_data); + $display("%t: DRAM Wr Req: addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen, dram_req_data); else - $display("%t: DRAM Rd Req: rw=%b addr=%0h, tag=%0h, byteen=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen); + $display("%t: DRAM Rd Req: addr=%0h, tag=%0h, byteen=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen); end if (dram_rsp_valid && dram_rsp_ready) begin $display("%t: DRAM Rsp: tag=%0h, data=%0h", $time, dram_rsp_tag, dram_rsp_data); diff --git a/hw/rtl/libs/VX_dp_ram.v b/hw/rtl/libs/VX_dp_ram.v index 9c9366cc..07a188dc 100644 --- a/hw/rtl/libs/VX_dp_ram.v +++ b/hw/rtl/libs/VX_dp_ram.v @@ -7,7 +7,6 @@ module VX_dp_ram #( parameter BYTEENW = 1, parameter BUFFERED = 1, parameter RWCHECK = 1, - parameter RWBYPASS = 0, parameter ADDRW = $clog2(SIZE), parameter SIZEW = $clog2(SIZE+1), parameter FASTRAM = 0 @@ -48,35 +47,9 @@ module VX_dp_ram #( always @(posedge clk) begin if (rden) dout_r <= mem[raddr]; - end + end - if (RWBYPASS) begin - reg [DATAW-1:0] din_r; - wire writing; - - if (BYTEENW > 1) begin - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8]; - end - end - end - end else begin - always @(posedge clk) begin - din_r <= din; - end - end - - reg bypass_r; - always @(posedge clk) begin - bypass_r <= wren && (raddr == waddr); - end - - assign dout = bypass_r ? din_r : dout_r; - end else begin assign dout = dout_r; - end end else begin @@ -102,37 +75,11 @@ module VX_dp_ram #( end end - if (RWBYPASS) begin - reg [DATAW-1:0] din_r; - wire writing; - - if (BYTEENW > 1) begin - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8]; - end - end - end - end else begin - always @(posedge clk) begin - din_r <= din; - end - end - - reg bypass_r; - always @(posedge clk) begin - bypass_r <= writing && (raddr == waddr); - end - - assign dout = bypass_r ? din_r : mem[raddr]; - end else begin assign dout = mem[raddr]; - end end else begin - `USE_FAST_BRAM `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0]; + `USE_FAST_BRAM `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0]; if (BYTEENW > 1) begin always @(posedge clk) begin @@ -181,33 +128,7 @@ module VX_dp_ram #( dout_r <= mem[raddr]; end - if (RWBYPASS) begin - reg [DATAW-1:0] din_r; - wire writing; - - if (BYTEENW > 1) begin - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8]; - end - end - end - end else begin - always @(posedge clk) begin - din_r <= din; - end - end - - reg bypass_r; - always @(posedge clk) begin - bypass_r <= wren && (raddr == waddr); - end - - assign dout = bypass_r ? din_r : dout_r; - end else begin assign dout = dout_r; - end end else begin @@ -233,33 +154,7 @@ module VX_dp_ram #( end end - if (RWBYPASS) begin - reg [DATAW-1:0] din_r; - wire writing; - - if (BYTEENW > 1) begin - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8]; - end - end - end - end else begin - always @(posedge clk) begin - din_r <= din; - end - end - - reg bypass_r; - always @(posedge clk) begin - bypass_r <= writing && (raddr == waddr); - end - - assign dout = bypass_r ? din_r : mem[raddr]; - end else begin assign dout = mem[raddr]; - end end else begin @@ -280,6 +175,7 @@ module VX_dp_ram #( mem[waddr] <= din; end end + assign dout = mem[raddr]; end end