From efac643c6681b0b1623081e5c7adb29f8d000c84 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 29 Mar 2020 02:11:14 -0700 Subject: [PATCH] Added Proper Handshaking to Everything and Fixed a Couple of Bugs --- rtl/VX_cache/VX_bank.v | 16 +- rtl/VX_cache/VX_cache.v | 5 +- rtl/VX_cache/VX_cache_dram_req_arb.v | 8 +- rtl/VX_define.v | 11 +- rtl/VX_dmem_controller.v | 3 + rtl/Vortex.v | 7 + rtl/Vortex_Cluster.v | 300 +++++++ rtl/Vortex_SOC.v | 796 ++++-------------- rtl/interfaces/VX_gpu_dcache_dram_req_inter.v | 4 + 9 files changed, 523 insertions(+), 627 deletions(-) create mode 100644 rtl/Vortex_Cluster.v diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 904f2593..759b8a65 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -331,14 +331,14 @@ module VX_bank mrvq_hazard_st0 = 0; reqq_hazard_st0 = 0; snrq_hazard_st0 = 0; - for (st1_cycle = 0; st1_cycle < STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin - if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin - if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) dfpq_hazard_st0 = 1; - if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) mrvq_hazard_st0 = 1; - if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) reqq_hazard_st0 = 1; - if (snrq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) snrq_hazard_st0 = 1; - end - end + // for (st1_cycle = 0; st1_cycle < STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin + // if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin + // if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) dfpq_hazard_st0 = 1; + // if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) mrvq_hazard_st0 = 1; + // if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) reqq_hazard_st0 = 1; + // if (snrq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) snrq_hazard_st0 = 1; + // end + // end end wire qual_is_fill_st0; diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 05b01f37..6d206b0f 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -91,6 +91,8 @@ module VX_cache output wire [31:0] dram_req_size, output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data, output wire dram_req_because_of_wb, + input wire dram_req_delay, + output wire dram_snp_full, @@ -183,7 +185,8 @@ module VX_cache .dram_req_addr (dram_req_addr), .dram_req_size (dram_req_size), .dram_req_data (dram_req_data), - .dram_req_because_of_wb (dram_req_because_of_wb) + .dram_req_because_of_wb (dram_req_because_of_wb), + .dram_req_delay (dram_req_delay) ); diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v index 119ea9ad..2fbd5389 100644 --- a/rtl/VX_cache/VX_cache_dram_req_arb.v +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -68,7 +68,9 @@ module VX_cache_dram_req_arb output wire [31:0] dram_req_addr, output wire [31:0] dram_req_size, output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data, - output wire dram_req_because_of_wb + output wire dram_req_because_of_wb, + + input wire dram_req_delay ); @@ -76,7 +78,7 @@ module VX_cache_dram_req_arb wire[31:0] dfqq_req_addr; wire dfqq_empty; wire dwb_valid; - wire dfqq_pop = !dwb_valid && dfqq_req; // If no dwb, and dfqq has valids, then pop + wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_delay; // If no dwb, and dfqq has valids, then pop wire dfqq_push = (|per_bank_dram_fill_req); VX_cache_dfq_queue VX_cache_dfq_queue( @@ -101,7 +103,7 @@ module VX_cache_dram_req_arb ); - assign per_bank_dram_wb_queue_pop = per_bank_dram_wb_req & ((1 << dwb_bank)); + assign per_bank_dram_wb_queue_pop = dram_req_delay ? 0 : per_bank_dram_wb_req & ((1 << dwb_bank)); assign dram_req = dwb_valid || dfqq_req; diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 5e6dae1a..17f34734 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -20,7 +20,6 @@ `endif // `define QUEUE_FORCE_MLAB 1 -// `define L3C 1 `define NT_M1 (`NT-1) @@ -261,7 +260,7 @@ // Dram knobs `ifndef DSIMULATED_DRAM_LATENCY_CYCLES -`define DSIMULATED_DRAM_LATENCY_CYCLES 10 +`define DSIMULATED_DRAM_LATENCY_CYCLES 2 `endif // ========================================= Icache Configurable Knobs ========================================= @@ -369,7 +368,7 @@ // Dram knobs `ifndef ISIMULATED_DRAM_LATENCY_CYCLES -`define ISIMULATED_DRAM_LATENCY_CYCLES 10 +`define ISIMULATED_DRAM_LATENCY_CYCLES 2 `endif // ========================================= SM Configurable Knobs ========================================= @@ -475,7 +474,7 @@ // Dram knobs `ifndef SSIMULATED_DRAM_LATENCY_CYCLES -`define SSIMULATED_DRAM_LATENCY_CYCLES 10 +`define SSIMULATED_DRAM_LATENCY_CYCLES 2 `endif // ========================================= L2cache Configurable Knobs ========================================= @@ -580,7 +579,7 @@ // Dram knobs `ifndef LLSIMULATED_DRAM_LATENCY_CYCLES -`define LLSIMULATED_DRAM_LATENCY_CYCLES 10 +`define LLSIMULATED_DRAM_LATENCY_CYCLES 2 `endif // ========================================= L3cache Configurable Knobs ========================================= @@ -685,7 +684,7 @@ // Dram knobs `ifndef L3SIMULATED_DRAM_LATENCY_CYCLES -`define L3SIMULATED_DRAM_LATENCY_CYCLES 10 +`define L3SIMULATED_DRAM_LATENCY_CYCLES 2 `endif // VX_DEFINE diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index b9cff01b..c8f7b761 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -144,6 +144,7 @@ module VX_dmem_controller ( .dram_req_addr (VX_gpu_smem_dram_req.dram_req_addr), .dram_req_size (VX_gpu_smem_dram_req.dram_req_size), .dram_req_data (VX_gpu_smem_dram_req.dram_req_data), + .dram_req_delay (1), // Snoop Response .dram_req_because_of_wb(VX_gpu_smem_dram_req.dram_because_of_snp), @@ -225,6 +226,7 @@ module VX_dmem_controller ( .dram_req_addr (VX_gpu_dcache_dram_req.dram_req_addr), .dram_req_size (VX_gpu_dcache_dram_req.dram_req_size), .dram_req_data (VX_gpu_dcache_dram_req.dram_req_data), + .dram_req_delay (VX_gpu_dcache_dram_req.dram_req_delay), // Snoop Response .dram_req_because_of_wb(VX_gpu_dcache_dram_req.dram_because_of_snp), @@ -310,6 +312,7 @@ module VX_dmem_controller ( .dram_req_addr (VX_gpu_icache_dram_req.dram_req_addr), .dram_req_size (VX_gpu_icache_dram_req.dram_req_size), .dram_req_data (VX_gpu_icache_dram_req.dram_req_data), + .dram_req_delay (VX_gpu_icache_dram_req.dram_req_delay), // Snoop Response .dram_req_because_of_wb(VX_gpu_icache_dram_req.dram_because_of_snp), diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 282c5c54..4e4b6dff 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -24,6 +24,8 @@ module Vortex output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG], output wire [31:0] dram_expected_lat, + input wire dram_req_delay, + // DRAM Dcache Res output wire dram_fill_accept, input wire dram_fill_rsp, @@ -95,6 +97,7 @@ module Vortex input wire [31:0] I_dram_fill_rsp_addr, input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data, + input wire dram_req_delay, input wire snp_req, input wire [31:0] snp_req_addr, @@ -140,6 +143,8 @@ module Vortex assign dram_expected_lat = `DSIMULATED_DRAM_LATENCY_CYCLES; assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept; + assign VX_gpu_dcache_dram_req.dram_req_delay = dram_req_delay; + genvar wordy; generate for (wordy = 0; wordy < `DBANK_LINE_SIZE_WORDS; wordy=wordy+1) begin @@ -183,6 +188,8 @@ module Vortex assign I_dram_expected_lat = `ISIMULATED_DRAM_LATENCY_CYCLES; assign I_dram_fill_accept = VX_gpu_icache_dram_req.dram_fill_accept; + assign VX_gpu_icache_dram_req.dram_req_delay = dram_req_delay; + genvar iwordy; generate for (iwordy = 0; iwordy < `IBANK_LINE_SIZE_WORDS; iwordy=iwordy+1) begin diff --git a/rtl/Vortex_Cluster.v b/rtl/Vortex_Cluster.v new file mode 100644 index 00000000..c5ae3baa --- /dev/null +++ b/rtl/Vortex_Cluster.v @@ -0,0 +1,300 @@ +`include "VX_define.v" +`include "VX_cache_config.v" + + +module Vortex_Cluster + #( + parameter CLUSTER_ID = 0 + ) + ( + + // Clock + input wire clk, + input wire reset, + + // IO + output wire[`NUMBER_CORES_PER_CLUSTER-1:0] io_valid, + output wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] io_data, + + // DRAM Req + output wire out_dram_req, + output wire out_dram_req_write, + output wire out_dram_req_read, + output wire [31:0] out_dram_req_addr, + output wire [31:0] out_dram_req_size, + output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG], + output wire [31:0] out_dram_expected_lat, + input wire out_dram_req_delay, + + // DRAM Res + output wire out_dram_fill_accept, + input wire out_dram_fill_rsp, + input wire [31:0] out_dram_fill_rsp_addr, + input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + + + // LLC Snooping + input wire llc_snp_req, + input wire llc_snp_req_addr, + output wire llc_snp_req_delay, + + output wire out_ebreak +); + + // DRAM Dcache Req + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_write; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_read; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_addr; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_size; + wire[`NUMBER_CORES_PER_CLUSTER-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_req_data; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_expected_lat; + + // DRAM Dcache Res + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_fill_accept; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_fill_rsp; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_fill_rsp_addr; + wire[`NUMBER_CORES_PER_CLUSTER-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_fill_rsp_data; + + + // DRAM Icache Req + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_write; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_read; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_addr; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_size; + wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_req_data; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_expected_lat; + + // DRAM Icache Res + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_accept; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_rsp; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr; + wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data; + + // Out ebreak + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_out_ebreak; + + + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_io_valid; + wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_io_data; + + + wire l2c_core_accept; + + + wire snp_fwd; + wire[31:0] snp_fwd_addr; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] snp_fwd_delay; + + assign out_ebreak = (&per_core_out_ebreak); + + genvar curr_core; + generate + + for (curr_core = 0; curr_core < `NUMBER_CORES_PER_CLUSTER; curr_core=curr_core+1) begin + + wire [`IBANK_LINE_SIZE_RNG][31:0] curr_core_I_dram_req_data; + wire [`DBANK_LINE_SIZE_RNG][31:0] curr_core_dram_req_data ; + + assign io_valid[curr_core] = per_core_io_valid[curr_core]; + assign io_data [curr_core] = per_core_io_data [curr_core]; + + Vortex #(.CORE_ID(curr_core + (CLUSTER_ID * `NUMBER_CORES_PER_CLUSTER))) vortex_core( + .clk (clk), + .reset (reset), + .io_valid (per_core_io_valid [curr_core]), + .io_data (per_core_io_data [curr_core]), + .dram_req (per_core_dram_req [curr_core]), + .dram_req_write (per_core_dram_req_write [curr_core]), + .dram_req_read (per_core_dram_req_read [curr_core]), + .dram_req_addr (per_core_dram_req_addr [curr_core]), + .dram_req_size (per_core_dram_req_size [curr_core]), + .dram_req_data (curr_core_dram_req_data ), + .dram_expected_lat (per_core_dram_expected_lat [curr_core]), + .dram_fill_accept (per_core_dram_fill_accept [curr_core]), + .dram_fill_rsp (per_core_dram_fill_rsp [curr_core]), + .dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]), + .dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]), + .I_dram_req (per_core_I_dram_req [curr_core]), + .I_dram_req_write (per_core_I_dram_req_write [curr_core]), + .I_dram_req_read (per_core_I_dram_req_read [curr_core]), + .I_dram_req_addr (per_core_I_dram_req_addr [curr_core]), + .I_dram_req_size (per_core_I_dram_req_size [curr_core]), + .I_dram_req_data (curr_core_I_dram_req_data ), + .I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]), + .I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]), + .I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]), + .I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]), + .I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]), + .dram_req_delay (l2c_core_accept ), + .out_ebreak (per_core_out_ebreak [curr_core]), + .snp_req (snp_fwd), + .snp_req_addr (snp_fwd_addr), + .snp_req_delay (snp_fwd_delay[curr_core]), + .I_snp_req (0), + .I_snp_req_addr (), + .I_snp_req_delay () + ); + + assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data; + assign per_core_I_dram_req_data[curr_core] = curr_core_I_dram_req_data; + end + endgenerate + + + //////////////////// L2 Cache //////////////////// + wire[`LLNUMBER_REQUESTS-1:0] l2c_core_req; + wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write; + wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read; + wire[`LLNUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr; + wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_core_req_data; + wire[`LLNUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb; + + wire[`LLNUMBER_REQUESTS-1:0] l2c_core_no_wb_slot; + + + + wire[`LLNUMBER_REQUESTS-1:0] l2c_wb; + wire[`LLNUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr; + wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_wb_data; + + + wire[`DBANK_LINE_SIZE_RNG][31:0] dram_req_data_port; + wire[`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data_port; + + genvar llb_index; + generate + for (llb_index = 0; llb_index < `DBANK_LINE_SIZE_WORDS; llb_index=llb_index+1) begin + assign out_dram_req_data [llb_index] = dram_req_data_port[llb_index]; + assign dram_fill_rsp_data_port[llb_index] = out_dram_fill_rsp_data[llb_index]; + end + endgenerate + + + // + genvar l2c_curr_core; + generate + for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin + // Core Request + assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)]; + assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)]; + + assign l2c_core_req_mem_write [l2c_curr_core] = per_core_dram_req_write[(l2c_curr_core/2)] ? `SW_MEM_WRITE : `NO_MEM_WRITE; + assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write + + assign l2c_core_req_mem_read [l2c_curr_core] = per_core_dram_req_read[(l2c_curr_core/2)] ? `LW_MEM_READ : `NO_MEM_READ; + assign l2c_core_req_mem_read [l2c_curr_core+1] = `LW_MEM_READ; // I caches don't write + + assign l2c_core_req_wb [l2c_curr_core] = per_core_dram_req_read[(l2c_curr_core/2)] ? 1 : 0; + assign l2c_core_req_wb [l2c_curr_core+1] = 1; // I caches don't write + + assign l2c_core_req_addr [l2c_curr_core] = per_core_dram_req_addr [(l2c_curr_core/2)]; + assign l2c_core_req_addr [l2c_curr_core+1] = per_core_I_dram_req_addr[(l2c_curr_core/2)]; + + assign l2c_core_req_data [l2c_curr_core] = per_core_dram_req_data [(l2c_curr_core/2)]; + assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)]; + + // Core can't accept Response + assign l2c_core_no_wb_slot [l2c_curr_core] = ~per_core_dram_fill_accept [(l2c_curr_core/2)]; + assign l2c_core_no_wb_slot [l2c_curr_core+1] = ~per_core_I_dram_fill_accept[(l2c_curr_core/2)]; + + // Cache Fill Response + assign per_core_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core]; + assign per_core_I_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1]; + + assign per_core_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core]; + assign per_core_I_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1]; + + assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core]; + assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1]; + end + endgenerate + + wire dram_snp_full; + wire dram_req_because_of_wb; + VX_cache #( + .CACHE_SIZE_BYTES (`LLCACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (`LLNUMBER_BANKS), + .WORD_SIZE_BYTES (`LLWORD_SIZE_BYTES), + .NUMBER_REQUESTS (`LLNUMBER_REQUESTS), + .STAGE_1_CYCLES (`LLSTAGE_1_CYCLES), + .FUNC_ID (`LLFUNC_ID), + .REQQ_SIZE (`LLREQQ_SIZE), + .MRVQ_SIZE (`LLMRVQ_SIZE), + .DFPQ_SIZE (`LLDFPQ_SIZE), + .SNRQ_SIZE (`LLSNRQ_SIZE), + .CWBQ_SIZE (`LLCWBQ_SIZE), + .DWBQ_SIZE (`LLDWBQ_SIZE), + .DFQQ_SIZE (`LLDFQQ_SIZE), + .LLVQ_SIZE (`LLLLVQ_SIZE), + .FFSQ_SIZE (`LLFFSQ_SIZE), + .FILL_INVALIDAOR_SIZE (`LLFILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(`LLSIMULATED_DRAM_LATENCY_CYCLES) + ) + gpu_l2cache + ( + .clk (clk), + .reset (reset), + + // Core Req (DRAM Fills/WB) To L2 Request + .core_req_valid (l2c_core_req), + .core_req_addr (l2c_core_req_addr), + .core_req_writedata({l2c_core_req_data}), + .core_req_mem_read (l2c_core_req_mem_read), + .core_req_mem_write(l2c_core_req_mem_write), + .core_req_rd (0), + .core_req_wb (l2c_core_req_wb), + .core_req_warp_num (0), + .core_req_pc (0), + + // L2 can't accept Core Request + .delay_req (l2c_core_accept), + + // Core can't accept L2 Request + .core_no_wb_slot (|l2c_core_no_wb_slot), + + // Core Writeback + .core_wb_valid (l2c_wb), + .core_wb_req_rd (), + .core_wb_req_wb (), + .core_wb_warp_num (), + .core_wb_readdata ({l2c_wb_data}), + .core_wb_address (l2c_wb_addr), + .core_wb_pc (), + + // L2 Cache DRAM Fill response + .dram_fill_rsp (out_dram_fill_rsp), + .dram_fill_rsp_addr(out_dram_fill_rsp_addr), + .dram_fill_rsp_data({dram_fill_rsp_data_port}), + + // L2 Cache can't accept Fill Response + .dram_fill_accept (out_dram_fill_accept), + + // L2 Cache DRAM Fill Request + .dram_req (out_dram_req), + .dram_req_write (out_dram_req_write), + .dram_req_read (out_dram_req_read), + .dram_req_addr (out_dram_req_addr), + .dram_req_size (out_dram_req_size), + .dram_req_data ({dram_req_data_port}), + .dram_req_delay (out_dram_req_delay), + + // Snoop Response + .dram_req_because_of_wb(dram_req_because_of_wb), + .dram_snp_full (dram_snp_full), + + // Snoop Request + .snp_req (llc_snp_req), + .snp_req_addr (llc_snp_req_addr), + .snp_req_delay (llc_snp_req_delay), + + .snp_fwd (snp_fwd), + .snp_fwd_addr (snp_fwd_addr), + .snp_fwd_delay (|snp_fwd_delay) + ); + + + +endmodule \ No newline at end of file diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v index a58b6830..ddd1f6c1 100644 --- a/rtl/Vortex_SOC.v +++ b/rtl/Vortex_SOC.v @@ -21,6 +21,7 @@ module Vortex_SOC ( output wire [31:0] out_dram_req_size, output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG], output wire [31:0] out_dram_expected_lat, + input wire out_dram_req_delay, // DRAM Res output wire out_dram_fill_accept, @@ -36,694 +37,271 @@ module Vortex_SOC ( output wire out_ebreak ); -`ifdef L3C - - // DRAM Dcache Req - wire [`NUMBER_CLUSTERS-1:0] dram_req; - wire [`NUMBER_CLUSTERS-1:0] dram_req_write; - wire [`NUMBER_CLUSTERS-1:0] dram_req_read; - wire [`NUMBER_CLUSTERS-1:0][31:0] dram_req_addr; - wire [`NUMBER_CLUSTERS-1:0][31:0] dram_req_size; - wire [`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG][31:0] dram_req_data; - wire [`NUMBER_CLUSTERS-1:0][31:0] dram_expected_lat; - - // DRAM Dcache Res - wire [`NUMBER_CLUSTERS-1:0] dram_fill_accept; - wire [`NUMBER_CLUSTERS-1:0] dram_fill_rsp; - wire [`NUMBER_CLUSTERS-1:0][31:0] dram_fill_rsp_addr; - wire [`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data; - assign number_cores = `NUMBER_CORES; - // Out ebreak - wire[`NUMBER_CORES-1:0] per_core_out_ebreak; - assign out_ebreak = (&per_core_out_ebreak); - wire[`L3NUMBER_REQUESTS-1:0] l3c_core_req; - wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_write; - wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_read; - wire[`L3NUMBER_REQUESTS-1:0][31:0] l3c_core_req_addr; - wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_core_req_data; - wire[`L3NUMBER_REQUESTS-1:0][1:0] l3c_core_req_wb; + if (`NUMBER_CLUSTERS == 1) begin - wire l3c_core_accept; - - wire l3c_snp_fwd; - wire[31:0] l3c_snp_fwd_addr; - wire[`L3NUMBER_REQUESTS-1:0] l3c_snp_fwd_delay_temp; - wire l3c_snp_fwd_delay; - - assign l3c_snp_fwd_delay = (|l3c_snp_fwd_delay_temp); + wire[`NUMBER_CORES-1:0] cluster_io_valid; + wire[`NUMBER_CORES-1:0][31:0] cluster_io_data; - wire[`L3NUMBER_REQUESTS-1:0] l3c_wb; - wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr; - wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_wb_data; - - wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_req_data; - wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_fill_rsp_data; - - genvar curr_l; - generate - for (curr_l = 0; curr_l < `IBANK_LINE_SIZE_WORDS; curr_l=curr_l+1) begin - assign out_dram_req_data[curr_l][31:0] = l3c_dram_req_data[curr_l][31:0]; - assign l3c_dram_fill_rsp_data[curr_l][31:0] = out_dram_fill_rsp_data[curr_l][31:0]; + genvar curr_c; + for (curr_c = 0; curr_c < `NUMBER_CORES; curr_c=curr_c+1) begin + assign io_valid[curr_c] = cluster_io_valid[curr_c]; + assign io_data [curr_c] = cluster_io_data [curr_c]; end - endgenerate - // - genvar l3c_curr_core; - generate - for (l3c_curr_core = 0; l3c_curr_core < `L3NUMBER_REQUESTS; l3c_curr_core=l3c_curr_core+1) begin - // Core Request - assign l3c_core_req [l3c_curr_core] = dram_req [(l3c_curr_core)]; + Vortex_Cluster #(.CLUSTER_ID(0)) Vortex_Cluster( + .clk (clk), + .reset (reset), + .io_valid (cluster_io_valid), + .io_data (cluster_io_data), + + .out_dram_req (out_dram_req), + .out_dram_req_write (out_dram_req_write), + .out_dram_req_read (out_dram_req_read), + .out_dram_req_addr (out_dram_req_addr), + .out_dram_req_size (out_dram_req_size), + .out_dram_req_data (out_dram_req_data), + .out_dram_expected_lat (out_dram_expected_lat), + .out_dram_req_delay (out_dram_req_delay), - assign l3c_core_req_mem_write [l3c_curr_core] = dram_req_write ? `SW_MEM_WRITE : `NO_MEM_WRITE; + .out_dram_fill_accept (out_dram_fill_accept), + .out_dram_fill_rsp (out_dram_fill_rsp), + .out_dram_fill_rsp_addr(out_dram_fill_rsp_addr), + .out_dram_fill_rsp_data(out_dram_fill_rsp_data), - assign l3c_core_req_mem_read [l3c_curr_core] = dram_req_read ? `LW_MEM_READ : `NO_MEM_READ; + .llc_snp_req (llc_snp_req), + .llc_snp_req_addr (llc_snp_req_addr), + .llc_snp_req_delay (llc_snp_req_delay), + .out_ebreak (out_ebreak) + ); + end else begin - assign l3c_core_req_wb [l3c_curr_core] = dram_req_read ? 1 : 0; + wire snp_fwd; + wire[31:0] snp_fwd_addr; + wire[`NUMBER_CLUSTERS-1:0] snp_fwd_delay; - assign l3c_core_req_addr [l3c_curr_core] = dram_req_addr [(l3c_curr_core)]; + wire[`NUMBER_CLUSTERS-1:0] per_cluster_out_ebreak; - assign l3c_core_req_data [l3c_curr_core] = dram_req_data [(l3c_curr_core)]; - - // L2 can't accept requests - assign dram_fill_accept [(l3c_curr_core)] = l3c_core_accept; - - // Cache Fill Response - assign dram_fill_rsp [(l3c_curr_core)] = l3c_wb[l3c_curr_core]; - - assign dram_fill_rsp_data[(l3c_curr_core)] = l3c_wb_data[l3c_curr_core]; - - assign dram_fill_rsp_addr[(l3c_curr_core)] = l3c_wb_addr[l3c_curr_core]; - end - endgenerate - - wire dram_snp_full; - wire dram_req_because_of_wb; + assign out_ebreak = (&per_cluster_out_ebreak); - VX_cache #( - .CACHE_SIZE_BYTES (`L3CACHE_SIZE_BYTES), - .BANK_LINE_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (`L3NUMBER_BANKS), - .WORD_SIZE_BYTES (`L3WORD_SIZE_BYTES), - .NUMBER_REQUESTS (`L3NUMBER_REQUESTS), - .STAGE_1_CYCLES (`L3STAGE_1_CYCLES), - .FUNC_ID (`LLFUNC_ID), - .REQQ_SIZE (`L3REQQ_SIZE), - .MRVQ_SIZE (`L3MRVQ_SIZE), - .DFPQ_SIZE (`L3DFPQ_SIZE), - .SNRQ_SIZE (`L3SNRQ_SIZE), - .CWBQ_SIZE (`L3CWBQ_SIZE), - .DWBQ_SIZE (`L3DWBQ_SIZE), - .DFQQ_SIZE (`L3DFQQ_SIZE), - .LLVQ_SIZE (`L3LLVQ_SIZE), - .FFSQ_SIZE (`L3FFSQ_SIZE), - .FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE), - .SIMULATED_DRAM_LATENCY_CYCLES(`L3SIMULATED_DRAM_LATENCY_CYCLES) - ) - gpu_l3cache - ( - .clk (clk), - .reset (reset), + // // DRAM Dcache Req + wire[`NUMBER_CLUSTERS-1:0] per_cluster_dram_req; + wire[`NUMBER_CLUSTERS-1:0] per_cluster_dram_req_write; + wire[`NUMBER_CLUSTERS-1:0] per_cluster_dram_req_read; + wire[`NUMBER_CLUSTERS-1:0] [31:0] per_cluster_dram_req_addr; + wire[`NUMBER_CLUSTERS-1:0] [31:0] per_cluster_dram_req_size; + wire[`NUMBER_CLUSTERS-1:0] [31:0] per_cluster_dram_expected_lat; + wire[`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_cluster_dram_req_data; + wire[31:0] per_cluster_dram_req_data_up[`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG]; - // Core Req (DRAM Fills/WB) To L2 Request - .core_req_valid (l3c_core_req), - .core_req_addr (l3c_core_req_addr), - .core_req_writedata({l3c_core_req_data}), - .core_req_mem_read (l3c_core_req_mem_read), - .core_req_mem_write(l3c_core_req_mem_write), - .core_req_rd (0), - .core_req_wb (l3c_core_req_wb), - .core_req_warp_num (0), - .core_req_pc (0), + wire l3c_core_accept; - // L2 can't accept Core Request - .delay_req (l3c_core_accept), + // // DRAM Dcache Res + wire[`NUMBER_CLUSTERS-1:0] per_cluster_dram_fill_accept; + wire[`NUMBER_CLUSTERS-1:0] per_cluster_dram_fill_rsp; + wire[`NUMBER_CLUSTERS-1:0] [31:0] per_cluster_dram_fill_rsp_addr; + wire[`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_cluster_dram_fill_rsp_data; + wire[31:0] per_cluster_dram_fill_rsp_data_up[`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG]; - // Core can't accept L2 Request - .core_no_wb_slot (0), + wire[`NUMBER_CLUSTERS-1:0][`NUMBER_CORES_PER_CLUSTER-1:0] per_cluster_io_valid; + wire[`NUMBER_CLUSTERS-1:0][`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_cluster_io_data; - // Core Writeback - .core_wb_valid (l3c_wb), - .core_wb_req_rd (), - .core_wb_req_wb (), - .core_wb_warp_num (), - .core_wb_readdata ({l3c_wb_data}), - .core_wb_address (l3c_wb_addr), - .core_wb_pc (), - - // L2 Cache DRAM Fill response - .dram_fill_rsp (out_dram_fill_rsp), - .dram_fill_rsp_addr(out_dram_fill_rsp_addr), - .dram_fill_rsp_data({l3c_dram_fill_rsp_data}), - - // L2 Cache can't accept Fill Response - .dram_fill_accept (out_dram_fill_accept), - - // L2 Cache DRAM Fill Request - .dram_req (out_dram_req), - .dram_req_write (out_dram_req_write), - .dram_req_read (out_dram_req_read), - .dram_req_addr (out_dram_req_addr), - .dram_req_size (out_dram_req_size), - .dram_req_data ({l3c_dram_req_data}), - - // Snoop Response - .dram_req_because_of_wb(dram_req_because_of_wb), - .dram_snp_full (dram_snp_full), - - // Snoop Request - .snp_req (llc_snp_req), - .snp_req_addr (llc_snp_req_addr), - .snp_req_delay (llc_snp_req_delay), - - .snp_fwd (l3c_snp_fwd), - .snp_fwd_addr (l3c_snp_fwd_addr), - .snp_fwd_delay (l3c_snp_fwd_delay) - ); - - - - //////////////////// L3 Cache //////////////////// - - - - genvar curr_cluster; - genvar curr_core; - genvar llb_index; - genvar l2c_curr_core; - - generate - for (curr_cluster = 0; curr_cluster < `NUMBER_CLUSTERS; curr_cluster=curr_cluster+1) begin - ////////////////////// BEGIN CLUSTER ///////////////// - - // DRAM Dcache Req - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_write; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_read; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_addr; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_size; - wire[`NUMBER_CORES_PER_CLUSTER-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_req_data; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_expected_lat; - - // DRAM Dcache Res - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_fill_accept; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_fill_rsp; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_fill_rsp_addr; - wire[`NUMBER_CORES_PER_CLUSTER-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_fill_rsp_data; - - - // DRAM Icache Req - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_write; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_read; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_addr; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_size; - wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_req_data; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_expected_lat; - - // DRAM Icache Res - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_accept; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_rsp; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr; - wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data; - - // Snoop Requests - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dcache_snp_req; - wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_dcache_snp_req_addr; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dcache_snp_req_delay; - - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_icache_snp_req; - wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_icache_snp_req_addr; - wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_icache_snp_req_delay; - - // generate - for (curr_core = 0; curr_core < `NUMBER_CORES_PER_CLUSTER; curr_core=curr_core+1) begin - - wire [`IBANK_LINE_SIZE_RNG][31:0] curr_core_I_dram_req_data; - wire [`DBANK_LINE_SIZE_RNG][31:0] curr_core_dram_req_data ; - - // assign io_valid[curr_core*curr_cluster] = per_core_io_valid[curr_core]; - // assign io_data [curr_core*curr_cluster] = per_core_io_data [curr_core]; - Vortex #(.CORE_ID(curr_core+(curr_cluster*`NUMBER_CORES_PER_CLUSTER))) vortex_core( - .clk (clk), - .reset (reset), - .io_valid (io_valid [curr_core+(curr_cluster*`NUMBER_CORES_PER_CLUSTER)]), - .io_data (io_data [curr_core+(curr_cluster*`NUMBER_CORES_PER_CLUSTER)]), - .out_ebreak (per_core_out_ebreak [curr_core+(curr_cluster*`NUMBER_CORES_PER_CLUSTER)]), - .dram_req (per_core_dram_req [curr_core]), - .dram_req_write (per_core_dram_req_write [curr_core]), - .dram_req_read (per_core_dram_req_read [curr_core]), - .dram_req_addr (per_core_dram_req_addr [curr_core]), - .dram_req_size (per_core_dram_req_size [curr_core]), - .dram_req_data (curr_core_dram_req_data ), - .dram_expected_lat (per_core_dram_expected_lat [curr_core]), - .dram_fill_accept (per_core_dram_fill_accept [curr_core]), - .dram_fill_rsp (per_core_dram_fill_rsp [curr_core]), - .dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]), - .dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]), - .I_dram_req (per_core_I_dram_req [curr_core]), - .I_dram_req_write (per_core_I_dram_req_write [curr_core]), - .I_dram_req_read (per_core_I_dram_req_read [curr_core]), - .I_dram_req_addr (per_core_I_dram_req_addr [curr_core]), - .I_dram_req_size (per_core_I_dram_req_size [curr_core]), - .I_dram_req_data (curr_core_I_dram_req_data ), - .I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]), - .I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]), - .I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]), - .I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]), - .I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]), - .snp_req (per_core_dcache_snp_req [curr_core]), - .snp_req_addr (per_core_dcache_snp_req_addr [curr_core]), - .snp_req_delay (per_core_dcache_snp_req_delay[curr_core]), - .I_snp_req (per_core_icache_snp_req [curr_core]), - .I_snp_req_addr (per_core_icache_snp_req_addr [curr_core]), - .I_snp_req_delay (per_core_icache_snp_req_delay[curr_core]) - ); - - assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data; - assign per_core_I_dram_req_data[curr_core] = curr_core_I_dram_req_data; + genvar curr_c; + genvar curr_cc; + genvar curr_word; + for (curr_c = 0; curr_c < `NUMBER_CLUSTERS; curr_c =curr_c+1) begin + for (curr_cc = 0; curr_cc < `NUMBER_CORES_PER_CLUSTER; curr_cc=curr_cc+1) begin + assign io_valid[curr_cc+(curr_c*`NUMBER_CORES_PER_CLUSTER)] = per_cluster_io_valid[curr_c][curr_cc]; + assign io_data [curr_cc+(curr_c*`NUMBER_CORES_PER_CLUSTER)] = per_cluster_io_data [curr_c][curr_cc]; end - // endgenerate - //////////////////// L2 Cache //////////////////// - wire[`LLNUMBER_REQUESTS-1:0] l2c_core_req; - wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write; - wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read; - wire[`LLNUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr; - wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_core_req_data; - wire[`LLNUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb; + for (curr_word = 0; curr_word < `DBANK_LINE_SIZE_WORDS; curr_word = curr_word+1) begin + assign per_cluster_dram_req_data [curr_c][curr_word] = per_cluster_dram_req_data_up [curr_c][curr_word]; + assign per_cluster_dram_fill_rsp_data_up[curr_c][curr_word] = per_cluster_dram_fill_rsp_data[curr_c][curr_word]; + end - wire l2c_core_accept; - - wire l2c_snp_fwd; - wire[31:0] l2c_snp_fwd_addr; - wire l2c_snp_fwd_delay; - - assign l2c_snp_fwd_delay = (|per_core_dcache_snp_req_delay) || (|per_core_icache_snp_req_delay); + end - wire[`LLNUMBER_REQUESTS-1:0] l2c_wb; - wire[`LLNUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr; - wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_wb_data; - // endgenerate + genvar curr_cluster; + for (curr_cluster = 0; curr_cluster < `NUMBER_CLUSTERS; curr_cluster=curr_cluster+1) begin - // generate - for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin + Vortex_Cluster #(.CLUSTER_ID(curr_cluster)) Vortex_Cluster( + .clk (clk), + .reset (reset), + .io_valid (per_cluster_io_valid [curr_cluster]), + .io_data (per_cluster_io_data [curr_cluster]), + + .out_dram_req (per_cluster_dram_req [curr_cluster]), + .out_dram_req_write (per_cluster_dram_req_write [curr_cluster]), + .out_dram_req_read (per_cluster_dram_req_read [curr_cluster]), + .out_dram_req_addr (per_cluster_dram_req_addr [curr_cluster]), + .out_dram_req_size (per_cluster_dram_req_size [curr_cluster]), + .out_dram_req_data (per_cluster_dram_req_data_up [curr_cluster]), + .out_dram_expected_lat (per_cluster_dram_expected_lat [curr_cluster]), + .out_dram_req_delay (l3c_core_accept), + + .out_dram_fill_accept (per_cluster_dram_fill_accept [curr_cluster]), + .out_dram_fill_rsp (per_cluster_dram_fill_rsp [curr_cluster]), + .out_dram_fill_rsp_addr(per_cluster_dram_fill_rsp_addr [curr_cluster]), + .out_dram_fill_rsp_data(per_cluster_dram_fill_rsp_data_up[curr_cluster]), + + .llc_snp_req (snp_fwd), + .llc_snp_req_addr (snp_fwd_addr), + .llc_snp_req_delay (snp_fwd_delay[curr_cluster]), + + .out_ebreak (per_cluster_out_ebreak [curr_cluster]) + ); + end + + + //////////////////// L3 Cache //////////////////// + wire[`L3NUMBER_REQUESTS-1:0] l3c_core_req; + wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_write; + wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_read; + wire[`L3NUMBER_REQUESTS-1:0][31:0] l3c_core_req_addr; + wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_core_req_data; + wire[`L3NUMBER_REQUESTS-1:0][1:0] l3c_core_req_wb; + + wire[`L3NUMBER_REQUESTS-1:0] l3c_core_no_wb_slot; + + + + wire[`L3NUMBER_REQUESTS-1:0] l3c_wb; + wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr; + wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_wb_data; + + + wire[`DBANK_LINE_SIZE_RNG][31:0] dram_req_data_port; + wire[`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data_port; + + genvar llb_index; + for (llb_index = 0; llb_index < `DBANK_LINE_SIZE_WORDS; llb_index=llb_index+1) begin + assign out_dram_req_data [llb_index] = dram_req_data_port[llb_index]; + assign dram_fill_rsp_data_port[llb_index] = out_dram_fill_rsp_data[llb_index]; + end + + + // + genvar l3c_curr_cluster; + for (l3c_curr_cluster = 0; l3c_curr_cluster < `L3NUMBER_REQUESTS; l3c_curr_cluster=l3c_curr_cluster+1) begin // Core Request - assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)]; - assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)]; + assign l3c_core_req [l3c_curr_cluster] = per_cluster_dram_req [l3c_curr_cluster]; - assign l2c_core_req_mem_write [l2c_curr_core] = per_core_dram_req_write ? `SW_MEM_WRITE : `NO_MEM_WRITE; - assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write + assign l3c_core_req_mem_write [l3c_curr_cluster] = per_cluster_dram_req_write[l3c_curr_cluster] ? `SW_MEM_WRITE : `NO_MEM_WRITE; - assign l2c_core_req_mem_read [l2c_curr_core] = per_core_dram_req_read ? `LW_MEM_READ : `NO_MEM_READ; - assign l2c_core_req_mem_read [l2c_curr_core+1] = `LW_MEM_READ; // I caches don't write + assign l3c_core_req_mem_read [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? `LW_MEM_READ : `NO_MEM_READ; - assign l2c_core_req_wb [l2c_curr_core] = per_core_dram_req_read ? 1 : 0; - assign l2c_core_req_wb [l2c_curr_core+1] = 1; // I caches don't write + assign l3c_core_req_wb [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? 1 : 0; - assign l2c_core_req_addr [l2c_curr_core] = per_core_dram_req_addr [(l2c_curr_core/2)]; - assign l2c_core_req_addr [l2c_curr_core+1] = per_core_I_dram_req_addr[(l2c_curr_core/2)]; + assign l3c_core_req_addr [l3c_curr_cluster] = per_cluster_dram_req_addr [l3c_curr_cluster]; - assign l2c_core_req_data [l2c_curr_core] = per_core_dram_req_data [(l2c_curr_core/2)]; - assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)]; + assign l3c_core_req_data [l3c_curr_cluster] = per_cluster_dram_req_data [l3c_curr_cluster]; - // L2 can't accept requests - assign per_core_dram_fill_accept [(l2c_curr_core/2)] = l2c_core_accept; - assign per_core_I_dram_fill_accept[(l2c_curr_core/2)] = l2c_core_accept; + // Core can't accept Response + assign l3c_core_no_wb_slot [l3c_curr_cluster] = ~per_cluster_dram_fill_accept[l3c_curr_cluster]; // Cache Fill Response - assign per_core_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core]; - assign per_core_I_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1]; + assign per_cluster_dram_fill_rsp [l3c_curr_cluster] = l3c_wb [l3c_curr_cluster]; + assign per_cluster_dram_fill_rsp_data[l3c_curr_cluster] = l3c_wb_data[l3c_curr_cluster]; + assign per_cluster_dram_fill_rsp_addr[l3c_curr_cluster] = l3c_wb_addr[l3c_curr_cluster]; - assign per_core_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core]; - assign per_core_I_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1]; - - assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core]; - assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1]; - - assign per_core_dcache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd; - assign per_core_dcache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr; - - assign per_core_icache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd; - assign per_core_icache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr; end - // endgenerate wire dram_snp_full; wire dram_req_because_of_wb; - - VX_cache #( - .CACHE_SIZE_BYTES (`LLCACHE_SIZE_BYTES), - .BANK_LINE_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (`LLNUMBER_BANKS), - .WORD_SIZE_BYTES (`LLWORD_SIZE_BYTES), - .NUMBER_REQUESTS (`LLNUMBER_REQUESTS), - .STAGE_1_CYCLES (`LLSTAGE_1_CYCLES), + .CACHE_SIZE_BYTES (`L3CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (`L3NUMBER_BANKS), + .WORD_SIZE_BYTES (`L3WORD_SIZE_BYTES), + .NUMBER_REQUESTS (`L3NUMBER_REQUESTS), + .STAGE_1_CYCLES (`L3STAGE_1_CYCLES), .FUNC_ID (`LLFUNC_ID), - .REQQ_SIZE (`LLREQQ_SIZE), - .MRVQ_SIZE (`LLMRVQ_SIZE), - .DFPQ_SIZE (`LLDFPQ_SIZE), - .SNRQ_SIZE (`LLSNRQ_SIZE), - .CWBQ_SIZE (`LLCWBQ_SIZE), - .DWBQ_SIZE (`LLDWBQ_SIZE), - .DFQQ_SIZE (`LLDFQQ_SIZE), - .LLVQ_SIZE (`LLLLVQ_SIZE), - .FFSQ_SIZE (`LLFFSQ_SIZE), - .FILL_INVALIDAOR_SIZE (`LLFILL_INVALIDAOR_SIZE), - .SIMULATED_DRAM_LATENCY_CYCLES(`LLSIMULATED_DRAM_LATENCY_CYCLES) + .REQQ_SIZE (`L3REQQ_SIZE), + .MRVQ_SIZE (`L3MRVQ_SIZE), + .DFPQ_SIZE (`L3DFPQ_SIZE), + .SNRQ_SIZE (`L3SNRQ_SIZE), + .CWBQ_SIZE (`L3CWBQ_SIZE), + .DWBQ_SIZE (`L3DWBQ_SIZE), + .DFQQ_SIZE (`L3DFQQ_SIZE), + .LLVQ_SIZE (`L3LLVQ_SIZE), + .FFSQ_SIZE (`L3FFSQ_SIZE), + .FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(`L3SIMULATED_DRAM_LATENCY_CYCLES) ) - gpu_l2cache + gpu_l3cache ( .clk (clk), .reset (reset), // Core Req (DRAM Fills/WB) To L2 Request - .core_req_valid (l2c_core_req), - .core_req_addr (l2c_core_req_addr), - .core_req_writedata({l2c_core_req_data}), - .core_req_mem_read (l2c_core_req_mem_read), - .core_req_mem_write(l2c_core_req_mem_write), + .core_req_valid (l3c_core_req), + .core_req_addr (l3c_core_req_addr), + .core_req_writedata({l3c_core_req_data}), + .core_req_mem_read (l3c_core_req_mem_read), + .core_req_mem_write(l3c_core_req_mem_write), .core_req_rd (0), - .core_req_wb (l2c_core_req_wb), + .core_req_wb (l3c_core_req_wb), .core_req_warp_num (0), .core_req_pc (0), // L2 can't accept Core Request - .delay_req (l2c_core_accept), + .delay_req (l3c_core_accept), // Core can't accept L2 Request - .core_no_wb_slot (0), + .core_no_wb_slot (|l3c_core_no_wb_slot), // Core Writeback - .core_wb_valid (l2c_wb), + .core_wb_valid (l3c_wb), .core_wb_req_rd (), .core_wb_req_wb (), .core_wb_warp_num (), - .core_wb_readdata ({l2c_wb_data}), - .core_wb_address (l2c_wb_addr), + .core_wb_readdata ({l3c_wb_data}), + .core_wb_address (l3c_wb_addr), .core_wb_pc (), // L2 Cache DRAM Fill response - .dram_fill_rsp (dram_fill_rsp[curr_cluster]), - .dram_fill_rsp_addr(dram_fill_rsp_addr[curr_cluster]), - .dram_fill_rsp_data({dram_fill_rsp_data[curr_cluster]}), + .dram_fill_rsp (out_dram_fill_rsp), + .dram_fill_rsp_addr(out_dram_fill_rsp_addr), + .dram_fill_rsp_data({dram_fill_rsp_data_port}), // L2 Cache can't accept Fill Response - .dram_fill_accept (dram_fill_accept), + .dram_fill_accept (out_dram_fill_accept), // L2 Cache DRAM Fill Request - .dram_req (dram_req[curr_cluster]), - .dram_req_write (dram_req_write[curr_cluster]), - .dram_req_read (dram_req_read[curr_cluster]), - .dram_req_addr (dram_req_addr[curr_cluster]), - .dram_req_size (dram_req_size[curr_cluster]), - .dram_req_data ({dram_req_data[curr_cluster]}), + .dram_req (out_dram_req), + .dram_req_write (out_dram_req_write), + .dram_req_read (out_dram_req_read), + .dram_req_addr (out_dram_req_addr), + .dram_req_size (out_dram_req_size), + .dram_req_data ({dram_req_data_port}), + .dram_req_delay (out_dram_req_delay), // Snoop Response .dram_req_because_of_wb(dram_req_because_of_wb), .dram_snp_full (dram_snp_full), // Snoop Request - .snp_req (l3c_snp_fwd), - .snp_req_addr (l3c_snp_fwd_addr), - .snp_req_delay (l3c_snp_fwd_delay_temp[curr_cluster]), + .snp_req (llc_snp_req), + .snp_req_addr (llc_snp_req_addr), + .snp_req_delay (llc_snp_req_delay), - .snp_fwd (l2c_snp_fwd), - .snp_fwd_addr (l2c_snp_fwd_addr), - .snp_fwd_delay (l2c_snp_fwd_delay) + // Snoop Forward + .snp_fwd (snp_fwd), + .snp_fwd_addr (snp_fwd_addr), + .snp_fwd_delay (|snp_fwd_delay) ); - // // Snoop Request - // .snp_req (VX_gpu_icache_snp_req.snp_req), - // .snp_req_addr (VX_gpu_icache_snp_req.snp_req_addr), - // .snp_req_delay (VX_gpu_icache_snp_req.snp_delay), + end - //////////////////// L2 Cache //////////////////// - - - //////////////////// END CLUSTER /////////////////// - end - endgenerate - -`else - - assign number_cores = `NUMBER_CORES; - - // IO - wire per_core_io_valid[`NUMBER_CORES-1:0]; - wire[31:0] per_core_io_data[`NUMBER_CORES-1:0]; - - // DRAM Dcache Req - wire[`NUMBER_CORES-1:0] per_core_dram_req; - wire[`NUMBER_CORES-1:0] per_core_dram_req_write; - wire[`NUMBER_CORES-1:0] per_core_dram_req_read; - wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_req_addr; - wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_req_size; - wire[`NUMBER_CORES-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_req_data; - wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_expected_lat; - - // DRAM Dcache Res - wire[`NUMBER_CORES-1:0] per_core_dram_fill_accept; - wire[`NUMBER_CORES-1:0] per_core_dram_fill_rsp; - wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_fill_rsp_addr; - wire[`NUMBER_CORES-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_fill_rsp_data; - - - // DRAM Icache Req - wire[`NUMBER_CORES-1:0] per_core_I_dram_req; - wire[`NUMBER_CORES-1:0] per_core_I_dram_req_write; - wire[`NUMBER_CORES-1:0] per_core_I_dram_req_read; - wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_req_addr; - wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_req_size; - wire[`NUMBER_CORES-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_req_data; - wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_expected_lat; - - // DRAM Icache Res - wire[`NUMBER_CORES-1:0] per_core_I_dram_fill_accept; - wire[`NUMBER_CORES-1:0] per_core_I_dram_fill_rsp; - wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_fill_rsp_addr; - wire[`NUMBER_CORES-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data; - - // Out ebreak - wire[`NUMBER_CORES-1:0] per_core_out_ebreak; - - assign out_ebreak = (&per_core_out_ebreak); - - genvar curr_core; - generate - - for (curr_core = 0; curr_core < `NUMBER_CORES; curr_core=curr_core+1) begin - - wire [`IBANK_LINE_SIZE_RNG][31:0] curr_core_I_dram_req_data; - wire [`DBANK_LINE_SIZE_RNG][31:0] curr_core_dram_req_data ; - - assign io_valid[curr_core] = per_core_io_valid[curr_core]; - assign io_data [curr_core] = per_core_io_data [curr_core]; - - Vortex #(.CORE_ID(curr_core)) vortex_core( - .clk (clk), - .reset (reset), - .io_valid (per_core_io_valid [curr_core]), - .io_data (per_core_io_data [curr_core]), - .dram_req (per_core_dram_req [curr_core]), - .dram_req_write (per_core_dram_req_write [curr_core]), - .dram_req_read (per_core_dram_req_read [curr_core]), - .dram_req_addr (per_core_dram_req_addr [curr_core]), - .dram_req_size (per_core_dram_req_size [curr_core]), - .dram_req_data (curr_core_dram_req_data ), - .dram_expected_lat (per_core_dram_expected_lat [curr_core]), - .dram_fill_accept (per_core_dram_fill_accept [curr_core]), - .dram_fill_rsp (per_core_dram_fill_rsp [curr_core]), - .dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]), - .dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]), - .I_dram_req (per_core_I_dram_req [curr_core]), - .I_dram_req_write (per_core_I_dram_req_write [curr_core]), - .I_dram_req_read (per_core_I_dram_req_read [curr_core]), - .I_dram_req_addr (per_core_I_dram_req_addr [curr_core]), - .I_dram_req_size (per_core_I_dram_req_size [curr_core]), - .I_dram_req_data (curr_core_I_dram_req_data ), - .I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]), - .I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]), - .I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]), - .I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]), - .I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]), - .out_ebreak (per_core_out_ebreak [curr_core]) - ); - - assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data; - assign per_core_I_dram_req_data[curr_core] = curr_core_I_dram_req_data; - end - endgenerate - - - //////////////////// L2 Cache //////////////////// - wire[`LLNUMBER_REQUESTS-1:0] l2c_core_req; - wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write; - wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read; - wire[`LLNUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr; - wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_core_req_data; - wire[`LLNUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb; - - wire l2c_core_accept; - - - wire[`LLNUMBER_REQUESTS-1:0] l2c_wb; - wire[`LLNUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr; - wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_wb_data; - - - wire[`DBANK_LINE_SIZE_RNG][31:0] dram_req_data_port; - wire[`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data_port; - - genvar llb_index; - generate - for (llb_index = 0; llb_index < `DBANK_LINE_SIZE_WORDS; llb_index=llb_index+1) begin - assign out_dram_req_data [llb_index] = dram_req_data_port[llb_index]; - assign dram_fill_rsp_data_port[llb_index] = out_dram_fill_rsp_data[llb_index]; - end - endgenerate - - // genvar l2c_index; - // genvar l2c_bank_index; - // generate - // for (l2c_index = 0; l2c_index < `LLNUMBER_REQUESTS; l2c_index=l2c_index+1) begin - // assign l2c_wb [l2c_index] = l2c_wb_port [l2c_index]; - // assign l2c_wb_addr[l2c_index] = l2c_wb_addr_port[l2c_index]; - // for (l2c_bank_index = 0; l2c_bank_index < `LLNUMBER_REQUESTS; l2c_bank_index=l2c_bank_index+1) begin - // assign l2c_wb_data[l2c_index][l2c_bank_index] = l2c_wb_data_port[l2c_index][l2c_bank_index]; - // end - // end - // endgenerate - - // - genvar l2c_curr_core; - generate - for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin - // Core Request - assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)]; - assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)]; - - assign l2c_core_req_mem_write [l2c_curr_core] = per_core_dram_req_write ? `SW_MEM_WRITE : `NO_MEM_WRITE; - assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write - - assign l2c_core_req_mem_read [l2c_curr_core] = per_core_dram_req_read ? `LW_MEM_READ : `NO_MEM_READ; - assign l2c_core_req_mem_read [l2c_curr_core+1] = `LW_MEM_READ; // I caches don't write - - assign l2c_core_req_wb [l2c_curr_core] = per_core_dram_req_read ? 1 : 0; - assign l2c_core_req_wb [l2c_curr_core+1] = 1; // I caches don't write - - assign l2c_core_req_addr [l2c_curr_core] = per_core_dram_req_addr [(l2c_curr_core/2)]; - assign l2c_core_req_addr [l2c_curr_core+1] = per_core_I_dram_req_addr[(l2c_curr_core/2)]; - - assign l2c_core_req_data [l2c_curr_core] = per_core_dram_req_data [(l2c_curr_core/2)]; - assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)]; - - // L2 can't accept requests - assign per_core_dram_fill_accept [(l2c_curr_core/2)] = l2c_core_accept; - assign per_core_I_dram_fill_accept[(l2c_curr_core/2)] = l2c_core_accept; - - // Cache Fill Response - assign per_core_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core]; - assign per_core_I_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1]; - - assign per_core_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core]; - assign per_core_I_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1]; - - assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core]; - assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1]; - end - endgenerate - - wire dram_snp_full; - wire dram_req_because_of_wb; - VX_cache #( - .CACHE_SIZE_BYTES (`LLCACHE_SIZE_BYTES), - .BANK_LINE_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (`LLNUMBER_BANKS), - .WORD_SIZE_BYTES (`LLWORD_SIZE_BYTES), - .NUMBER_REQUESTS (`LLNUMBER_REQUESTS), - .STAGE_1_CYCLES (`LLSTAGE_1_CYCLES), - .FUNC_ID (`LLFUNC_ID), - .REQQ_SIZE (`LLREQQ_SIZE), - .MRVQ_SIZE (`LLMRVQ_SIZE), - .DFPQ_SIZE (`LLDFPQ_SIZE), - .SNRQ_SIZE (`LLSNRQ_SIZE), - .CWBQ_SIZE (`LLCWBQ_SIZE), - .DWBQ_SIZE (`LLDWBQ_SIZE), - .DFQQ_SIZE (`LLDFQQ_SIZE), - .LLVQ_SIZE (`LLLLVQ_SIZE), - .FFSQ_SIZE (`LLFFSQ_SIZE), - .FILL_INVALIDAOR_SIZE (`LLFILL_INVALIDAOR_SIZE), - .SIMULATED_DRAM_LATENCY_CYCLES(`LLSIMULATED_DRAM_LATENCY_CYCLES) - ) - gpu_l2cache - ( - .clk (clk), - .reset (reset), - - // Core Req (DRAM Fills/WB) To L2 Request - .core_req_valid (l2c_core_req), - .core_req_addr (l2c_core_req_addr), - .core_req_writedata({l2c_core_req_data}), - .core_req_mem_read (l2c_core_req_mem_read), - .core_req_mem_write(l2c_core_req_mem_write), - .core_req_rd (0), - .core_req_wb (l2c_core_req_wb), - .core_req_warp_num (0), - .core_req_pc (0), - - // L2 can't accept Core Request - .delay_req (l2c_core_accept), - - // Core can't accept L2 Request - .core_no_wb_slot (0), - - // Core Writeback - .core_wb_valid (l2c_wb), - .core_wb_req_rd (), - .core_wb_req_wb (), - .core_wb_warp_num (), - .core_wb_readdata ({l2c_wb_data}), - .core_wb_address (l2c_wb_addr), - .core_wb_pc (), - - // L2 Cache DRAM Fill response - .dram_fill_rsp (out_dram_fill_rsp), - .dram_fill_rsp_addr(out_dram_fill_rsp_addr), - .dram_fill_rsp_data({dram_fill_rsp_data_port}), - - // L2 Cache can't accept Fill Response - .dram_fill_accept (out_dram_fill_accept), - - // L2 Cache DRAM Fill Request - .dram_req (out_dram_req), - .dram_req_write (out_dram_req_write), - .dram_req_read (out_dram_req_read), - .dram_req_addr (out_dram_req_addr), - .dram_req_size (out_dram_req_size), - .dram_req_data ({dram_req_data_port}), - - // Snoop Response - .dram_req_because_of_wb(dram_req_because_of_wb), - .dram_snp_full (dram_snp_full), - - // Snoop Request - .snp_req (llc_snp_req), - .snp_req_addr (llc_snp_req_addr) - ); - -`endif - - endmodule \ No newline at end of file diff --git a/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v b/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v index c088b553..c6d4ea1c 100644 --- a/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v @@ -27,6 +27,10 @@ interface VX_gpu_dcache_dram_req_inter // DRAM Cache can't accept response wire dram_fill_accept; + + // DRAM Cache can't accept request + wire dram_req_delay; + endinterface