diff --git a/Dockerfile b/Dockerfile
new file mode 100644
index 00000000..4306413d
--- /dev/null
+++ b/Dockerfile
@@ -0,0 +1,74 @@
+# Dockerfile for setting up the development environment for vortex
+
+# Set base OS
+FROM ubuntu:18.04
+
+# Install dependencies
+RUN apt update && apt install -y \
+    # verilator dependencies
+    git perl python3 g++ libfl2 libfl-dev \
+    zlibc zlib1g zlib1g-dev \
+    ccache libgoogle-perftools-dev numactl perl-doc \
+    git autoconf flex bison \
+    # riscv-gnu-toolchain dependencies
+    autoconf automake autotools-dev curl python3 \
+    libmpc-dev libmpfr-dev libgmp-dev gawk build-essential \
+    bison flex texinfo gperf libtool patchutils bc zlib1g-dev \
+    libexpat-dev binutils build-essential libtool texinfo \
+    # riscv-isa-sim dependencies
+    device-tree-compiler 
+
+# set environment variables
+ENV RISCV32=/opt/riscv32
+ENV RISCV64=/opt/riscv64
+ENV VERILATOR_ROOT=/opt/verilator
+ENV PATH=$PATH:${RISCV32}/bin:${RISCV64}/bin:${RISCV64}/riscv64-unknown-elf/bin:${VERILATOR_ROOT}/bin/verilator
+
+# Install riscv-gnu-toolchain
+RUN git clone https://github.com/riscv/riscv-gnu-toolchain /tmp/riscv-gnu-toolchain
+RUN cd /tmp/riscv-gnu-toolchain; \
+    ./configure --prefix=${RISCV32} --with-arch=rv32imf --with-abi=ilp32f; \
+    make -j `nproc`
+RUN cd /tmp/riscv-gnu-toolchain; \
+    ./configure --prefix=${RISCV64} --with-arch=rv64imfd --with-abi=lp64d; \
+    make -j `nproc`
+RUN rm -rf /tmp/riscv-gnu-toolchain
+
+# Install riscv-isa-sim 
+RUN git clone https://github.com/riscv-software-src/riscv-isa-sim.git /tmp/riscv-isa-sim
+RUN cd /tmp/riscv-isa-sim; \
+    mkdir build
+RUN cd /tmp/riscv-isa-sim/build; \
+    ../configure --prefix=${RISCV64}
+RUN cd /tmp/riscv-isa-sim/build; \
+    make -j `nproc`; \
+    make install
+RUN rm -rf /tmp/riscv-isa-sim
+
+# Install riscv-pk
+RUN git clone https://github.com/riscv-software-src/riscv-pk.git /tmp/riscv-pk
+RUN cd /tmp/riscv-pk; \
+    mkdir build 
+RUN cd /tmp/riscv-pk/build; \
+    ../configure --prefix=${RISCV64} --host=riscv64-unknown-elf
+RUN cd /tmp/riscv-pk/build; \
+    make -j `nproc`; \
+    make install
+RUN rm -rf /tmp/riscv-pk
+
+# Install verilator
+RUN git clone https://github.com/verilator/verilator /tmp/verilator
+RUN cd /tmp/verilator; \
+    git pull; \
+    git checkout v4.040
+RUN cd /tmp/verilator; \
+    autoconf; \
+    ./configure --prefix=/opt/verilator
+RUN cd/tmp/verilator; \
+    make -j `nproc`; \
+    make install
+RUN rm -rf /tmp/verilator
+
+# set working directory
+WORKDIR /mnt
+
diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh
index b52a1ab2..beb14603 100644
--- a/hw/rtl/VX_config.vh
+++ b/hw/rtl/VX_config.vh
@@ -41,6 +41,7 @@
 `define L1_BLOCK_SIZE ((`L2_ENABLE || `L3_ENABLE) ? 16 : `MEM_BLOCK_SIZE)
 `endif
 
+// simx64
 `ifndef STARTUP_ADDR
 `define STARTUP_ADDR 32'h80000000
 `endif
diff --git a/sim/simX/core.cpp b/sim/simX/core.cpp
index d5c8f1b9..bea53717 100644
--- a/sim/simX/core.cpp
+++ b/sim/simX/core.cpp
@@ -322,9 +322,9 @@ void Core::barrier(int bar_id, int count, int warp_id) {
 }
 
 // simx64
-Word Core::icache_fetch(Addr addr) {
-  Word data;
-  mem_.read(&data, addr, sizeof(Word), 0);
+HalfWord Core::icache_fetch(Addr addr) {
+  HalfWord data;
+  mem_.read(&data, addr, sizeof(HalfWord), 0);
   return data;
 }
 
diff --git a/sim/simX/core.h b/sim/simX/core.h
index 84e4a60f..8940ea0d 100644
--- a/sim/simX/core.h
+++ b/sim/simX/core.h
@@ -67,7 +67,7 @@ public:
   void barrier(int bar_id, int count, int warp_id);
 
   // simx64
-  Word icache_fetch(Addr);
+  HalfWord icache_fetch(Addr);
   // simx64
   Word dcache_read(Addr, Size);
   // simx64
diff --git a/sim/simX/decode.cpp b/sim/simX/decode.cpp
index 5e9718d9..8b5b7f40 100644
--- a/sim/simX/decode.cpp
+++ b/sim/simX/decode.cpp
@@ -46,10 +46,10 @@ static const std::unordered_map<int, struct InstTableEntry_t> sc_instTable = {
 };
 
 static const char* op_string(const Instr &instr) {  
-  Word func3 = instr.getFunc3();
-  Word func7 = instr.getFunc7();
-  Word rs2   = instr.getRSrc(1);
-  Word imm   = instr.getImm();
+  HalfWord func3 = instr.getFunc3();
+  HalfWord func7 = instr.getFunc7();
+  HalfWord rs2   = instr.getRSrc(1);
+  HalfWord imm   = instr.getImm();
   switch (instr.getOpcode()) {
   case Opcode::NOP:        return "NOP";
   case Opcode::LUI_INST:   return "LUI";
@@ -273,7 +273,8 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
 }
 
 Decoder::Decoder(const ArchDef &arch) {
-  inst_s_   = arch.wsize() * 8;
+  // simx64
+  inst_s_   = arch.wsize() * 4;
   opcode_s_ = 7;
   reg_s_    = 5;
   func2_s_  = 2;
@@ -307,20 +308,21 @@ Decoder::Decoder(const ArchDef &arch) {
   v_imm_mask_  = 0x7ff;  
 }
 
-std::shared_ptr<Instr> Decoder::decode(uint32_t code, uint32_t PC) {  
+// simx64
+std::shared_ptr<Instr> Decoder::decode(HalfWord code, HalfWord PC) {  
   auto instr = std::make_shared<Instr>();
   Opcode op = (Opcode)((code >> shift_opcode_) & opcode_mask_);
   instr->setOpcode(op);
 
-  Word func3 = (code >> shift_func3_) & func3_mask_;
-  Word func6 = (code >> shift_func6_) & func6_mask_;
-  Word func7 = (code >> shift_func7_) & func7_mask_;
+  HalfWord func3 = (code >> shift_func3_) & func3_mask_;
+  HalfWord func6 = (code >> shift_func6_) & func6_mask_;
+  HalfWord func7 = (code >> shift_func7_) & func7_mask_;
 
   // simx64
-  long rd  = (code >> shift_rd_)  & reg_mask_;
-  long rs1 = (code >> shift_rs1_) & reg_mask_;
-  long rs2 = (code >> shift_rs2_) & reg_mask_;
-  long rs3 = (code >> shift_rs3_) & reg_mask_;
+  int rd  = (code >> shift_rd_)  & reg_mask_;
+  int rs1 = (code >> shift_rs1_) & reg_mask_;
+  int rs2 = (code >> shift_rs2_) & reg_mask_;
+  int rs3 = (code >> shift_rs3_) & reg_mask_;
 
   auto op_it = sc_instTable.find(op);
   if (op_it == sc_instTable.end()) {
@@ -392,7 +394,7 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code, uint32_t PC) {
       instr->setSrcReg(rs2);
     }
     instr->setFunc3(func3);
-    Word imeed = (func7 << reg_s_) | rd;
+    HalfWord imeed = (func7 << reg_s_) | rd;
     instr->setImm(signExt(imeed, 12, s_imm_mask_));
   } break;
 
@@ -400,11 +402,11 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code, uint32_t PC) {
     instr->setSrcReg(rs1);
     instr->setSrcReg(rs2);
     instr->setFunc3(func3);
-    Word bit_11   = rd & 0x1;
-    Word bits_4_1 = rd >> 1;
-    Word bit_10_5 = func7 & 0x3f;
-    Word bit_12   = func7 >> 6;
-    Word imeed = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
+    HalfWord bit_11   = rd & 0x1;
+    HalfWord bits_4_1 = rd >> 1;
+    HalfWord bit_10_5 = func7 & 0x3f;
+    HalfWord bit_12   = func7 >> 6;
+    HalfWord imeed = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
     instr->setImm(signExt(imeed, 13, b_imm_mask_));
   } break;
 
@@ -415,12 +417,12 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code, uint32_t PC) {
 
   case InstType::J_TYPE: {
     instr->setDestReg(rd);
-    Word unordered = code >> shift_func3_;
-    Word bits_19_12 = unordered & 0xff;
-    Word bit_11 = (unordered >> 8) & 0x1;
-    Word bits_10_1 = (unordered >> 9) & 0x3ff;
-    Word bit_20 = (unordered >> 19) & 0x1;
-    Word imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
+    HalfWord unordered = code >> shift_func3_;
+    HalfWord bits_19_12 = unordered & 0xff;
+    HalfWord bit_11 = (unordered >> 8) & 0x1;
+    HalfWord bits_10_1 = (unordered >> 9) & 0x3ff;
+    HalfWord bit_20 = (unordered >> 19) & 0x1;
+    HalfWord imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
     if (bit_20) {
       imeed |= ~j_imm_mask_;
     }
@@ -436,7 +438,7 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code, uint32_t PC) {
       if (func3 == 7) {
         instr->setImm(!(code >> shift_vset_));
         if (instr->getImm()) {
-          Word immed = (code >> shift_rs2_) & v_imm_mask_;
+          HalfWord immed = (code >> shift_rs2_) & v_imm_mask_;
           instr->setImm(immed);
           instr->setVlmul(immed & 0x3);
           instr->setVediv((immed >> 4) & 0x3);
diff --git a/sim/simX/decode.h b/sim/simX/decode.h
index 9189439c..27307afc 100644
--- a/sim/simX/decode.h
+++ b/sim/simX/decode.h
@@ -13,49 +13,49 @@ class Decoder {
 public:
   Decoder(const ArchDef &);    
   
-  std::shared_ptr<Instr> decode(uint32_t code, uint32_t PC);
+  std::shared_ptr<Instr> decode(HalfWord code, HalfWord PC);
 
 private:
 
-  Word inst_s_;
-  Word opcode_s_;
-  Word reg_s_;
-  Word func2_s_;
-  Word func3_s_;
-  Word shift_opcode_;
-  Word shift_rd_;
-  Word shift_rs1_;
-  Word shift_rs2_;
-  Word shift_rs3_;
-  Word shift_func2_;
-  Word shift_func3_;
-  Word shift_func7_;
-  Word shift_j_u_immed_;
-  Word shift_s_b_immed_;
-  Word shift_i_immed_;
+  HalfWord inst_s_;
+  HalfWord opcode_s_;
+  HalfWord reg_s_;
+  HalfWord func2_s_;
+  HalfWord func3_s_;
+  HalfWord shift_opcode_;
+  HalfWord shift_rd_;
+  HalfWord shift_rs1_;
+  HalfWord shift_rs2_;
+  HalfWord shift_rs3_;
+  HalfWord shift_func2_;
+  HalfWord shift_func3_;
+  HalfWord shift_func7_;
+  HalfWord shift_j_u_immed_;
+  HalfWord shift_s_b_immed_;
+  HalfWord shift_i_immed_;
 
-  Word reg_mask_;
-  Word func2_mask_;
-  Word func3_mask_;
-  Word func6_mask_;
-  Word func7_mask_;
-  Word opcode_mask_;
-  Word i_imm_mask_;
-  Word s_imm_mask_;
-  Word b_imm_mask_;
-  Word u_imm_mask_;
-  Word j_imm_mask_;
-  Word v_imm_mask_;
+  HalfWord reg_mask_;
+  HalfWord func2_mask_;
+  HalfWord func3_mask_;
+  HalfWord func6_mask_;
+  HalfWord func7_mask_;
+  HalfWord opcode_mask_;
+  HalfWord i_imm_mask_;
+  HalfWord s_imm_mask_;
+  HalfWord b_imm_mask_;
+  HalfWord u_imm_mask_;
+  HalfWord j_imm_mask_;
+  HalfWord v_imm_mask_;
 
   //Vector
-  Word shift_vset_;
-  Word shift_vset_immed_;
-  Word shift_vmask_;
-  Word shift_vmop_;
-  Word shift_vnf_;
-  Word shift_func6_;
-  Word vmask_s_;
-  Word mop_s_;
+  HalfWord shift_vset_;
+  HalfWord shift_vset_immed_;
+  HalfWord shift_vmask_;
+  HalfWord shift_vmop_;
+  HalfWord shift_vnf_;
+  HalfWord shift_func6_;
+  HalfWord vmask_s_;
+  HalfWord mop_s_;
 };
 
 }
\ No newline at end of file
diff --git a/sim/simX/execute.cpp b/sim/simX/execute.cpp
index 5f3e2aa3..39110b59 100644
--- a/sim/simX/execute.cpp
+++ b/sim/simX/execute.cpp
@@ -52,12 +52,13 @@ inline void update_fcrs(uint32_t fflags, Core* core, uint32_t tid, uint32_t wid)
 void Warp::execute(const Instr &instr, Pipeline *pipeline) {
   assert(tmask_.any());
 
-  Word nextPC = PC_ + core_->arch().wsize();
+  // simx64
+  Word nextPC = PC_ + 4;
   bool runOnce = false;
   
-  Word func3 = instr.getFunc3();
-  Word func6 = instr.getFunc6();
-  Word func7 = instr.getFunc7();
+  HalfWord func3 = instr.getFunc3();
+  HalfWord func6 = instr.getFunc6();
+  HalfWord func7 = instr.getFunc7();
 
   auto opcode = instr.getOpcode();
   int rdest  = instr.getRDest();
@@ -1689,7 +1690,8 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
     }
   }
 
-  PC_ += core_->arch().wsize();
+  // simx64
+  PC_ += 4;
   if (PC_ != nextPC) {
     D(3, "*** Next PC: " << std::hex << nextPC << std::dec);
     PC_ = nextPC;
diff --git a/sim/simX/instr.h b/sim/simX/instr.h
index 167082fd..77feaf5e 100644
--- a/sim/simX/instr.h
+++ b/sim/simX/instr.h
@@ -73,39 +73,39 @@ public:
   void setSrcFReg(int srcReg) { rsrc_type_[num_rsrcs_] = 2; rsrc_[num_rsrcs_++] = srcReg;  }
   void setDestVReg(int destReg) { rdest_type_ = 3; rdest_ = destReg; }
   void setSrcVReg(int srcReg) { rsrc_type_[num_rsrcs_] = 3; rsrc_[num_rsrcs_++] = srcReg;  }
-  void setFunc3(Word func3) { func3_ = func3; }
-  void setFunc7(Word func7) { func7_ = func7; }
-  void setImm(Word imm) { has_imm_ = true; imm_ = imm; }
-  void setVlsWidth(Word width) { vlsWidth_ = width; }
-  void setVmop(Word mop) { vMop_ = mop; }
-  void setVnf(Word nf) { vNf_ = nf; }
-  void setVmask(Word mask) { vmask_ = mask; }
-  void setVs3(Word vs) { vs3_ = vs; }
-  void setVlmul(Word lmul) { vlmul_ = 1 << lmul; }
-  void setVsew(Word sew) { vsew_ = 1 << (3+sew); }
-  void setVediv(Word ediv) { vediv_ = 1 << ediv; }
-  void setFunc6(Word func6) { func6_ = func6; }
+  void setFunc3(HalfWord func3) { func3_ = func3; }
+  void setFunc7(HalfWord func7) { func7_ = func7; }
+  void setImm(HalfWord imm) { has_imm_ = true; imm_ = imm; }
+  void setVlsWidth(HalfWord width) { vlsWidth_ = width; }
+  void setVmop(HalfWord mop) { vMop_ = mop; }
+  void setVnf(HalfWord nf) { vNf_ = nf; }
+  void setVmask(HalfWord mask) { vmask_ = mask; }
+  void setVs3(HalfWord vs) { vs3_ = vs; }
+  void setVlmul(HalfWord lmul) { vlmul_ = 1 << lmul; }
+  void setVsew(HalfWord sew) { vsew_ = 1 << (3+sew); }
+  void setVediv(HalfWord ediv) { vediv_ = 1 << ediv; }
+  void setFunc6(HalfWord func6) { func6_ = func6; }
 
   /* Getters used by encoders. */
   Opcode getOpcode() const { return opcode_; }
-  Word getFunc3() const { return func3_; }
-  Word getFunc6() const { return func6_; }
-  Word getFunc7() const { return func7_; }
+  HalfWord getFunc3() const { return func3_; }
+  HalfWord getFunc6() const { return func6_; }
+  HalfWord getFunc7() const { return func7_; }
   int getNRSrc() const { return num_rsrcs_; }
   int getRSrc(int i) const { return rsrc_[i]; }
   int getRSType(int i) const { return rsrc_type_[i]; }
   int getRDest() const { return rdest_; }  
   int getRDType() const { return rdest_type_; }  
   bool hasImm() const { return has_imm_; }
-  Word getImm() const { return imm_; }
-  Word getVlsWidth() const { return vlsWidth_; }
-  Word getVmop() const { return vMop_; }
-  Word getvNf() const { return vNf_; }
-  Word getVmask() const { return vmask_; }
-  Word getVs3() const { return vs3_; }
-  Word getVlmul() const { return vlmul_; }
-  Word getVsew() const { return vsew_; }
-  Word getVediv() const { return vediv_; }
+  HalfWord getImm() const { return imm_; }
+  HalfWord getVlsWidth() const { return vlsWidth_; }
+  HalfWord getVmop() const { return vMop_; }
+  HalfWord getvNf() const { return vNf_; }
+  HalfWord getVmask() const { return vmask_; }
+  HalfWord getVs3() const { return vs3_; }
+  HalfWord getVlmul() const { return vlmul_; }
+  HalfWord getVsew() const { return vsew_; }
+  HalfWord getVediv() const { return vediv_; }
 
 private:
 
@@ -120,23 +120,23 @@ private:
   int isrc_mask_;
   int fsrc_mask_;  
   int vsrc_mask_;
-  Word imm_;
+  HalfWord imm_;
   int rsrc_type_[MAX_REG_SOURCES];
   int rsrc_[MAX_REG_SOURCES];  
   int rdest_;
-  Word func3_;
-  Word func7_;
+  HalfWord func3_;
+  HalfWord func7_;
 
   //Vector
-  Word vmask_;
-  Word vlsWidth_;
-  Word vMop_;
-  Word vNf_;
-  Word vs3_;
-  Word vlmul_;
-  Word vsew_;
-  Word vediv_;
-  Word func6_;
+  HalfWord vmask_;
+  HalfWord vlsWidth_;
+  HalfWord vMop_;
+  HalfWord vNf_;
+  HalfWord vs3_;
+  HalfWord vlmul_;
+  HalfWord vsew_;
+  HalfWord vediv_;
+  HalfWord func6_;
 
   friend std::ostream &operator<<(std::ostream &, const Instr&);
 };
diff --git a/sim/simX/types.h b/sim/simX/types.h
index 94078e4b..f5729303 100644
--- a/sim/simX/types.h
+++ b/sim/simX/types.h
@@ -7,6 +7,7 @@
 namespace vortex {
 
 typedef uint8_t  Byte;
+// simx64
 typedef uint64_t Word;
 typedef int64_t  WordI;
 
@@ -15,8 +16,8 @@ typedef uint32_t HalfWord;
 typedef int32_t HalfWordI;
 
 // simx64
-typedef uint32_t Addr;
-typedef uint32_t Size;
+typedef uint64_t Addr;
+typedef uint64_t Size;
 
 typedef std::bitset<32> RegMask;
 
diff --git a/sim/simX/warp.cpp b/sim/simX/warp.cpp
index 883a09dd..754b1561 100644
--- a/sim/simX/warp.cpp
+++ b/sim/simX/warp.cpp
@@ -36,7 +36,7 @@ void Warp::step(Pipeline *pipeline) {
 
   /* Fetch and decode. */    
 
-  Word fetched = core_->icache_fetch(PC_);
+  HalfWord fetched = core_->icache_fetch(PC_);
   auto instr = core_->decoder().decode(fetched, PC_);
 
   // Update pipeline
diff --git a/tests/runtime/hello64/Makefile b/tests/runtime/hello64/Makefile
new file mode 100644
index 00000000..4f8812ca
--- /dev/null
+++ b/tests/runtime/hello64/Makefile
@@ -0,0 +1,40 @@
+RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
+RISCV64_TOOLCHAIN_PATH ?= /nethome/ssrivatsan8/riscv
+VORTEX_RT_PATH ?= $(realpath ../../../runtime)
+
+CC = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc
+AR = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc-ar
+DP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objdump
+CP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objcopy
+
+CFLAGS += -march=rv64i -mabi=lp64 -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections
+CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw
+
+LDFLAGS += -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link64.ld -Wl,--noinhibit-exec,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a
+
+PROJECT = hello64
+
+SRCS = main.cpp
+
+all: $(PROJECT).elf $(PROJECT).bin $(PROJECT).dump
+
+$(PROJECT).dump: $(PROJECT).elf
+	$(DP) -D $(PROJECT).elf > $(PROJECT).dump
+
+$(PROJECT).bin: $(PROJECT).elf
+	$(CP) -O binary $(PROJECT).elf $(PROJECT).bin
+
+$(PROJECT).elf: $(SRCS)
+	$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
+
+run-rtlsim: $(PROJECT).bin
+	../../../sim/rtlsim/rtlsim $(PROJECT).bin
+
+run-simx: $(PROJECT).bin
+	../../../sim/simX/simX -a rv64i -c 1 -i $(PROJECT).bin
+
+.depend: $(SRCS)
+	$(CC) $(CFLAGS) -MM $^ > .depend;
+
+clean:
+	rm -rf *.elf *.bin *.dump .depend 
diff --git a/tests/runtime/hello64/main.cpp b/tests/runtime/hello64/main.cpp
new file mode 100644
index 00000000..69904cfd
--- /dev/null
+++ b/tests/runtime/hello64/main.cpp
@@ -0,0 +1,8 @@
+#include <stdio.h>
+
+int main()
+{
+	printf("Hello World!\n");
+
+	return 0;
+}
\ No newline at end of file
diff --git a/tests/runtime/simple64/Makefile b/tests/runtime/simple64/Makefile
new file mode 100644
index 00000000..10ff5fef
--- /dev/null
+++ b/tests/runtime/simple64/Makefile
@@ -0,0 +1,40 @@
+RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
+RISCV64_TOOLCHAIN_PATH ?= /nethome/ssrivatsan8/riscv
+VORTEX_RT_PATH ?= $(realpath ../../../runtime)
+
+CC = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc
+AR = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc-ar
+DP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objdump
+CP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objcopy
+
+CFLAGS += -march=rv64i -mabi=lp64 -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections
+CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw
+
+LDFLAGS += -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link64.ld -Wl,--noinhibit-exec,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a
+
+PROJECT = simple64
+
+SRCS = main.cpp
+
+all: $(PROJECT).elf $(PROJECT).bin $(PROJECT).dump
+
+$(PROJECT).dump: $(PROJECT).elf
+	$(DP) -D $(PROJECT).elf > $(PROJECT).dump
+
+$(PROJECT).bin: $(PROJECT).elf
+	$(CP) -O binary $(PROJECT).elf $(PROJECT).bin
+
+$(PROJECT).elf: $(SRCS)
+	$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
+
+run-rtlsim: $(PROJECT).bin
+	../../../sim/rtlsim/rtlsim $(PROJECT).bin
+
+run-simx: $(PROJECT).bin
+	../../../sim/simX/simX -a rv64i -c 1 -i $(PROJECT).bin
+
+.depend: $(SRCS)
+	$(CC) $(CFLAGS) -MM $^ > .depend;
+
+clean:
+	rm -rf *.elf *.bin *.dump .depend 
diff --git a/tests/runtime/simple64/main.cpp b/tests/runtime/simple64/main.cpp
new file mode 100644
index 00000000..68e00b3a
--- /dev/null
+++ b/tests/runtime/simple64/main.cpp
@@ -0,0 +1,5 @@
+int main()
+{
+	int num=1+2;
+	return 0;
+}
\ No newline at end of file