From f0e257bc8e9a089fdcd35ef123de12f7e7555a08 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 23 Apr 2020 09:09:01 -0400 Subject: [PATCH] minor update --- hw/rtl/VX_dmem_ctrl.v | 24 ++++++++++++------------ hw/rtl/Vortex.v | 20 ++++++++++---------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/hw/rtl/VX_dmem_ctrl.v b/hw/rtl/VX_dmem_ctrl.v index 1c1a2e65..9b8ca9ca 100644 --- a/hw/rtl/VX_dmem_ctrl.v +++ b/hw/rtl/VX_dmem_ctrl.v @@ -6,12 +6,12 @@ module VX_dmem_ctrl ( // Dram <-> Dcache VX_gpu_dcache_dram_req_if gpu_dcache_dram_req_if, - VX_gpu_dcache_dram_rsp_if gpu_dcache_dram_res_if, + VX_gpu_dcache_dram_rsp_if gpu_dcache_dram_rsp_if, VX_gpu_snp_req_rsp_if gpu_dcache_snp_req_if, // Dram <-> Icache VX_gpu_dcache_dram_req_if gpu_icache_dram_req_if, - VX_gpu_dcache_dram_rsp_if gpu_icache_dram_res_if, + VX_gpu_dcache_dram_rsp_if gpu_icache_dram_rsp_if, VX_gpu_snp_req_rsp_if gpu_icache_snp_req_if, // Core <-> Dcache @@ -69,7 +69,7 @@ module VX_dmem_ctrl ( assign dcache_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready; VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_smem_dram_req_if(); - VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_smem_dram_res_if(); + VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_smem_dram_rsp_if(); VX_cache #( .CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES), @@ -125,9 +125,9 @@ module VX_dmem_ctrl ( `IGNORE_WARNINGS_END // DRAM response - .dram_rsp_valid (gpu_smem_dram_res_if.dram_rsp_valid), - .dram_rsp_addr (gpu_smem_dram_res_if.dram_rsp_addr), - .dram_rsp_data (gpu_smem_dram_res_if.dram_rsp_data), + .dram_rsp_valid (gpu_smem_dram_rsp_if.dram_rsp_valid), + .dram_rsp_addr (gpu_smem_dram_rsp_if.dram_rsp_addr), + .dram_rsp_data (gpu_smem_dram_rsp_if.dram_rsp_data), // DRAM accept response .dram_rsp_ready (gpu_smem_dram_req_if.dram_rsp_ready), @@ -208,9 +208,9 @@ module VX_dmem_ctrl ( `IGNORE_WARNINGS_END // DRAM response - .dram_rsp_valid (gpu_dcache_dram_res_if.dram_rsp_valid), - .dram_rsp_addr (gpu_dcache_dram_res_if.dram_rsp_addr), - .dram_rsp_data (gpu_dcache_dram_res_if.dram_rsp_data), + .dram_rsp_valid (gpu_dcache_dram_rsp_if.dram_rsp_valid), + .dram_rsp_addr (gpu_dcache_dram_rsp_if.dram_rsp_addr), + .dram_rsp_data (gpu_dcache_dram_rsp_if.dram_rsp_data), // DRAM accept response .dram_rsp_ready (gpu_dcache_dram_req_if.dram_rsp_ready), @@ -289,9 +289,9 @@ module VX_dmem_ctrl ( `IGNORE_WARNINGS_END // DRAM response - .dram_rsp_valid (gpu_icache_dram_res_if.dram_rsp_valid), - .dram_rsp_addr (gpu_icache_dram_res_if.dram_rsp_addr), - .dram_rsp_data (gpu_icache_dram_res_if.dram_rsp_data), + .dram_rsp_valid (gpu_icache_dram_rsp_if.dram_rsp_valid), + .dram_rsp_addr (gpu_icache_dram_rsp_if.dram_rsp_addr), + .dram_rsp_data (gpu_icache_dram_rsp_if.dram_rsp_data), // DRAM accept response .dram_rsp_ready (gpu_icache_dram_req_if.dram_rsp_ready), diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 191feeb7..fc018f67 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -69,10 +69,10 @@ module Vortex #( VX_gpu_dcache_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_req_qual_if(); VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_dcache_dram_req_if(); - VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_dcache_dram_res_if(); + VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_dcache_dram_rsp_if(); - assign gpu_dcache_dram_res_if.dram_rsp_valid = dram_rsp_valid; - assign gpu_dcache_dram_res_if.dram_rsp_addr = dram_rsp_addr; + assign gpu_dcache_dram_rsp_if.dram_rsp_valid = dram_rsp_valid; + assign gpu_dcache_dram_rsp_if.dram_rsp_addr = dram_rsp_addr; assign dram_req_write = gpu_dcache_dram_req_if.dram_req_write; assign dram_req_read = gpu_dcache_dram_req_if.dram_req_read; @@ -84,7 +84,7 @@ module Vortex #( genvar i; generate for (i = 0; i < `DBANK_LINE_WORDS; i=i+1) begin - assign gpu_dcache_dram_res_if.dram_rsp_data[i] = dram_rsp_data[i * 32 +: 32]; + assign gpu_dcache_dram_rsp_if.dram_rsp_data[i] = dram_rsp_data[i * 32 +: 32]; assign dram_req_data[i * 32 +: 32] = gpu_dcache_dram_req_if.dram_req_data[i]; end endgenerate @@ -115,10 +115,10 @@ module Vortex #( VX_gpu_dcache_req_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_req_if(); VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) gpu_icache_dram_req_if(); - VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) gpu_icache_dram_res_if(); + VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) gpu_icache_dram_rsp_if(); - assign gpu_icache_dram_res_if.dram_rsp_valid = I_dram_rsp_valid; - assign gpu_icache_dram_res_if.dram_rsp_addr = I_dram_rsp_addr; + assign gpu_icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid; + assign gpu_icache_dram_rsp_if.dram_rsp_addr = I_dram_rsp_addr; assign I_dram_req_write = gpu_icache_dram_req_if.dram_req_write; assign I_dram_req_read = gpu_icache_dram_req_if.dram_req_read; @@ -130,7 +130,7 @@ module Vortex #( genvar j; generate for (j = 0; j < `IBANK_LINE_WORDS; j = j + 1) begin - assign gpu_icache_dram_res_if.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32]; + assign gpu_icache_dram_rsp_if.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32]; assign I_dram_req_data[j * 32 +: 32] = gpu_icache_dram_req_if.dram_req_data[j]; end endgenerate @@ -204,12 +204,12 @@ VX_dmem_ctrl dmem_ctrl ( // Dram <-> Dcache .gpu_dcache_dram_req_if (gpu_dcache_dram_req_if), - .gpu_dcache_dram_res_if (gpu_dcache_dram_res_if), + .gpu_dcache_dram_rsp_if (gpu_dcache_dram_rsp_if), .gpu_dcache_snp_req_if (gpu_dcache_snp_req_if), // Dram <-> Icache .gpu_icache_dram_req_if (gpu_icache_dram_req_if), - .gpu_icache_dram_res_if (gpu_icache_dram_res_if), + .gpu_icache_dram_rsp_if (gpu_icache_dram_rsp_if), .gpu_icache_snp_req_if (gpu_icache_snp_req_if), // Core <-> Icache