diff --git a/driver/opae/vlsim/opae_sim.cpp b/driver/opae/vlsim/opae_sim.cpp index a97a8457..8346186d 100644 --- a/driver/opae/vlsim/opae_sim.cpp +++ b/driver/opae/vlsim/opae_sim.cpp @@ -94,6 +94,7 @@ opae_sim::~opae_sim() { } #ifdef VCD_OUTPUT trace_->close(); + delete trace_; #endif for (auto& buffer : host_buffers_) { __aligned_free(buffer.second.data); diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 81f052cd..8adc6eed 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -23,7 +23,6 @@ module VX_lsu_unit #( localparam MEM_ADDRW = 32 - MEM_ASHIFT; localparam REQ_ASHIFT = `CLOG2(`DWORD_SIZE); - localparam REQ_ADDRW = 32 - REQ_ASHIFT; localparam ADDR_TYPEW = `NC_ADDR_BITS + `SM_ENABLE; diff --git a/hw/rtl/afu/VX_avs_wrapper.v b/hw/rtl/afu/VX_avs_wrapper.v index d1417e07..f6c3e8fd 100644 --- a/hw/rtl/afu/VX_avs_wrapper.v +++ b/hw/rtl/afu/VX_avs_wrapper.v @@ -1,17 +1,15 @@ `include "VX_define.vh" -module VX_avs_wrapper #( - parameter NUM_BANKS = 1, +module VX_avs_wrapper #( parameter AVS_DATA_WIDTH = 1, parameter AVS_ADDR_WIDTH = 1, parameter AVS_BURST_WIDTH = 1, - parameter AVS_BANKS = 1, + parameter AVS_BANKS = 1, parameter REQ_TAG_WIDTH = 1, parameter RD_QUEUE_SIZE = 1, - parameter AVS_BYTEENW = (AVS_DATA_WIDTH / 8), - parameter RD_QUEUE_ADDR_WIDTH = $clog2(RD_QUEUE_SIZE+1), - parameter AVS_BANKS_BITS = $clog2(AVS_BANKS) + localparam AVS_BYTEENW = (AVS_DATA_WIDTH / 8), + localparam RD_QUEUE_ADDR_WIDTH = $clog2(RD_QUEUE_SIZE+1) ) ( input wire clk, input wire reset, @@ -32,40 +30,40 @@ module VX_avs_wrapper #( input wire mem_rsp_ready, // AVS bus - output wire [AVS_DATA_WIDTH-1:0] avs_writedata [NUM_BANKS], - input wire [AVS_DATA_WIDTH-1:0] avs_readdata [NUM_BANKS], - output wire [AVS_ADDR_WIDTH-1:0] avs_address [NUM_BANKS], - input wire avs_waitrequest [NUM_BANKS], - output wire avs_write [NUM_BANKS], - output wire avs_read [NUM_BANKS], - output wire [AVS_BYTEENW-1:0] avs_byteenable [NUM_BANKS], - output wire [AVS_BURST_WIDTH-1:0] avs_burstcount [NUM_BANKS], - input avs_readdatavalid [NUM_BANKS] + output wire [AVS_DATA_WIDTH-1:0] avs_writedata [AVS_BANKS], + input wire [AVS_DATA_WIDTH-1:0] avs_readdata [AVS_BANKS], + output wire [AVS_ADDR_WIDTH-1:0] avs_address [AVS_BANKS], + input wire avs_waitrequest [AVS_BANKS], + output wire avs_write [AVS_BANKS], + output wire avs_read [AVS_BANKS], + output wire [AVS_BYTEENW-1:0] avs_byteenable [AVS_BANKS], + output wire [AVS_BURST_WIDTH-1:0] avs_burstcount [AVS_BANKS], + input avs_readdatavalid [AVS_BANKS] ); - localparam BANK_ADDRW = `LOG2UP(NUM_BANKS); - localparam OUTPUT_REG = (NUM_BANKS > 2); + localparam BANK_ADDRW = `LOG2UP(AVS_BANKS); + localparam OUTPUT_REG = (AVS_BANKS > 2); // Requests handling - wire [NUM_BANKS-1:0] avs_reqq_push, avs_reqq_pop, avs_reqq_ready; - wire [NUM_BANKS-1:0][REQ_TAG_WIDTH-1:0] avs_reqq_tag_out; - wire [NUM_BANKS-1:0] req_queue_going_full; - wire [NUM_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size; + wire [AVS_BANKS-1:0] avs_reqq_push, avs_reqq_pop, avs_reqq_ready; + wire [AVS_BANKS-1:0][REQ_TAG_WIDTH-1:0] avs_reqq_tag_out; + wire [AVS_BANKS-1:0] req_queue_going_full; + wire [AVS_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size; wire [BANK_ADDRW-1:0] req_bank_sel; - if (NUM_BANKS >= 2) begin + if (AVS_BANKS >= 2) begin assign req_bank_sel = mem_req_addr[BANK_ADDRW-1:0]; end else begin assign req_bank_sel = 0; end - for (genvar i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < AVS_BANKS; i++) begin assign avs_reqq_ready[i] = !req_queue_going_full[i] && !avs_waitrequest[i]; assign avs_reqq_push[i] = mem_req_valid && !mem_req_rw && avs_reqq_ready[i] && (req_bank_sel == i); end - for (genvar i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < AVS_BANKS; i++) begin VX_pending_size #( .SIZE (RD_QUEUE_SIZE) ) pending_size ( @@ -98,7 +96,7 @@ module VX_avs_wrapper #( ); end - for (genvar i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < AVS_BANKS; i++) begin assign avs_read[i] = mem_req_valid && !mem_req_rw && !req_queue_going_full[i] && (req_bank_sel == i); assign avs_write[i] = mem_req_valid && mem_req_rw && !req_queue_going_full[i] && (req_bank_sel == i); assign avs_address[i] = mem_req_addr; @@ -107,7 +105,7 @@ module VX_avs_wrapper #( assign avs_burstcount[i] = AVS_BURST_WIDTH'(1); end - if (NUM_BANKS >= 2) begin + if (AVS_BANKS >= 2) begin assign mem_req_ready = avs_reqq_ready[req_bank_sel]; end else begin assign mem_req_ready = avs_reqq_ready; @@ -115,14 +113,14 @@ module VX_avs_wrapper #( // Responses handling - wire [NUM_BANKS-1:0] rsp_arb_valid_in; - wire [NUM_BANKS-1:0][AVS_DATA_WIDTH+REQ_TAG_WIDTH-1:0] rsp_arb_data_in; - wire [NUM_BANKS-1:0] rsp_arb_ready_in; + wire [AVS_BANKS-1:0] rsp_arb_valid_in; + wire [AVS_BANKS-1:0][AVS_DATA_WIDTH+REQ_TAG_WIDTH-1:0] rsp_arb_data_in; + wire [AVS_BANKS-1:0] rsp_arb_ready_in; - wire [NUM_BANKS-1:0][AVS_DATA_WIDTH-1:0] avs_rspq_data_out; - wire [NUM_BANKS-1:0] avs_rspq_empty; + wire [AVS_BANKS-1:0][AVS_DATA_WIDTH-1:0] avs_rspq_data_out; + wire [AVS_BANKS-1:0] avs_rspq_empty; - for (genvar i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < AVS_BANKS; i++) begin VX_fifo_queue #( .DATAW (AVS_DATA_WIDTH), .SIZE (RD_QUEUE_SIZE), @@ -142,14 +140,14 @@ module VX_avs_wrapper #( ); end - for (genvar i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < AVS_BANKS; i++) begin assign rsp_arb_valid_in[i] = !avs_rspq_empty[i]; assign rsp_arb_data_in[i] = {avs_rspq_data_out[i], avs_reqq_tag_out[i]}; assign avs_reqq_pop[i] = rsp_arb_valid_in[i] && rsp_arb_ready_in[i]; end VX_stream_arbiter #( - .NUM_REQS (NUM_BANKS), + .NUM_REQS (AVS_BANKS), .DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH), .BUFFERED (OUTPUT_REG ? 1 : 0) ) rsp_arb ( diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index d24baef8..fa81b296 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -558,7 +558,6 @@ VX_mem_arb #( //-- VX_avs_wrapper #( - .NUM_BANKS (NUM_LOCAL_MEM_BANKS), .AVS_DATA_WIDTH (LMEM_DATA_WIDTH), .AVS_ADDR_WIDTH (LMEM_ADDR_WIDTH), .AVS_BURST_WIDTH (LMEM_BURST_CTRW), diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index c13da3aa..e1b3a270 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -379,7 +379,6 @@ module VX_bank #( .WORD_SIZE (WORD_SIZE), .NUM_REQS (NUM_REQS), .MSHR_SIZE (MSHR_SIZE), - .ALM_FULL (MSHR_SIZE-2), .CORE_TAG_WIDTH (CORE_TAG_WIDTH) ) miss_resrv ( .clk (clk), diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.v index 342bc596..c5377fdc 100644 --- a/hw/rtl/cache/VX_miss_resrv.v +++ b/hw/rtl/cache/VX_miss_resrv.v @@ -16,8 +16,7 @@ module VX_miss_resrv #( // Size of a word in bytes parameter WORD_SIZE = 1, // Miss Reserv Queue Knob - parameter MSHR_SIZE = 1, - parameter ALM_FULL = (MSHR_SIZE-1), + parameter MSHR_SIZE = 1, // core request tag size parameter CORE_TAG_WIDTH = 1, diff --git a/hw/rtl/libs/VX_stream_arbiter.v b/hw/rtl/libs/VX_stream_arbiter.v index c01e17f0..7b527f55 100644 --- a/hw/rtl/libs/VX_stream_arbiter.v +++ b/hw/rtl/libs/VX_stream_arbiter.v @@ -19,8 +19,6 @@ module VX_stream_arbiter #( output wire [LANES-1:0][DATAW-1:0] data_out, input wire [LANES-1:0] ready_out ); - - localparam LOG_NUM_REQS = $clog2(NUM_REQS); if (NUM_REQS > 1) begin wire sel_valid; diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index 11a83262..14020940 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -67,6 +67,7 @@ Simulator::~Simulator() { } #ifdef VCD_OUTPUT trace_->close(); + delete trace_; #endif delete vortex_; }