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minor updates

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This commit is contained in:
Blaise Tine
2021-01-13 15:52:03 -08:00
parent 0e1650e1c2
commit f146178c2d
1 changed files with 0 additions and 6 deletions
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6
hw/rtl/cache/VX_bank.v vendored
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@@ -271,12 +271,6 @@ module VX_bank #(
.data_out ({addr_st0, wsel_st0, mem_rw_st0, byteen_st0, writeword_st0, req_tid_st0, tag_st0, filldata_st0})
);
always @(posedge clk) begin
/*if (valid_st0) begin
if (mshr_pop)
end*/
end
`ifdef DBG_CACHE_REQ_INFO
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st0, debug_wid_st0} = tag_st0[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];