quartus build fixes
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16
hw/rtl/cache/VX_cache_core_req_bank_sel.v
vendored
16
hw/rtl/cache/VX_cache_core_req_bank_sel.v
vendored
@@ -14,29 +14,33 @@ module VX_cache_core_req_bank_sel #(
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`IGNORE_WARNINGS_BEGIN
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input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
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`IGNORE_WARNINGS_END
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input wire [NUM_BANKS-1:0] per_bank_ready,
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output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid,
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input wire [NUM_BANKS-1:0] per_bank_ready,
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output wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid,
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output wire core_req_ready
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);
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reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid_r;
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if (NUM_BANKS == 1) begin
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always @(*) begin
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per_bank_valid = 0;
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per_bank_valid_r = 0;
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for (integer i = 0; i < NUM_REQUESTS; i++) begin
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per_bank_valid[0][i] = core_req_valid[i];
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per_bank_valid_r[0][i] = core_req_valid[i];
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end
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end
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assign core_req_ready = per_bank_ready;
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end else begin
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reg [NUM_BANKS-1:0] per_bank_ready_sel;
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always @(*) begin
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per_bank_valid = 0;
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per_bank_valid_r = 0;
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per_bank_ready_sel = {NUM_BANKS{1'b1}};
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for (integer i = 0; i < NUM_REQUESTS; i++) begin
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per_bank_valid[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i];
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per_bank_valid_r[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i];
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per_bank_ready_sel[core_req_addr[i][`BANK_SELECT_ADDR_RNG]] = 0;
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end
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end
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assign core_req_ready = & (per_bank_ready | per_bank_ready_sel);
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end
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assign per_bank_valid = per_bank_valid_r;
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endmodule
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