Define DBG_TRACE_CORE_PIPELINE_VCS for selective debug trace

2023-11-27 16:05:15 -08:00
parent 99207c862c
commit f41b50fc07
3 changed files with 3 additions and 3 deletions
--- a/hw/rtl/core/VX_decode.sv
+++ b/hw/rtl/core/VX_decode.sv
@@ -536,7 +536,7 @@ module VX_decode  #(
    
    assign fetch_if.ibuf_pop = decode_if.ibuf_pop;

-`ifdef DBG_TRACE_CORE_PIPELINE
+`ifdef DBG_TRACE_CORE_PIPELINE_VCS
    always @(posedge clk) begin
        if (decode_if.valid && decode_if.ready) begin
            `TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, instr=0x%0h, ex=", $time, CORE_ID, decode_if.data.wid, decode_if.data.PC, instr));