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Define DBG_TRACE_CORE_PIPELINE_VCS for selective debug trace

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This commit is contained in:
Hansung Kim
2023-11-27 16:05:15 -08:00
parent 99207c862c
commit f41b50fc07
3 changed files with 3 additions and 3 deletions
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2
hw/rtl/core/VX_commit.sv
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@@ -195,7 +195,7 @@ module VX_commit import VX_gpu_pkg::*; #(
end
assign sim_wb_value = sim_wb_value_r;
`ifdef DBG_TRACE_CORE_PIPELINE
`ifdef DBG_TRACE_CORE_PIPELINE_VCS
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
always @(posedge clk) begin
if (alu_commit_if[i].valid && alu_commit_if[i].ready) begin

2
hw/rtl/core/VX_decode.sv
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@@ -536,7 +536,7 @@ module VX_decode #(
assign fetch_if.ibuf_pop = decode_if.ibuf_pop;
`ifdef DBG_TRACE_CORE_PIPELINE
`ifdef DBG_TRACE_CORE_PIPELINE_VCS
always @(posedge clk) begin
if (decode_if.valid && decode_if.ready) begin
`TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, instr=0x%0h, ex=", $time, CORE_ID, decode_if.data.wid, decode_if.data.PC, instr));

2
hw/rtl/core/VX_dispatch.sv
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@@ -206,7 +206,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
end
`endif
`ifdef DBG_TRACE_CORE_PIPELINE
`ifdef DBG_TRACE_CORE_PIPELINE_VCS
for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
always @(posedge clk) begin
if (operands_if[i].valid && operands_if[i].ready) begin