diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index 4db50618..1b7cf111 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -86,40 +86,35 @@ module VX_alu_unit #( wire [31:0] br_dest = add_result[alu_req_if.tid]; wire [32:0] cmp_result = sub_result[alu_req_if.tid]; - wire [32:0] cmp_result_r; - wire is_br_op_r; -`IGNORE_WARNINGS_BEGIN - wire [`BR_BITS-1:0] br_op_r; -`IGNORE_WARNINGS_END + wire is_less = cmp_result[32]; + wire is_equal = ~(| cmp_result[31:0]); + + wire br_neg = `BR_NEG(br_op); + wire br_less = `BR_LESS(br_op); + wire br_static = `BR_STATIC(br_op); + wire br_taken = ((br_less ? is_less : is_equal) ^ br_neg) | br_static; // output + wire is_br_op_r; + wire stall_out = ~alu_commit_if.ready && alu_commit_if.valid; VX_pipe_register #( - .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `BR_BITS + 32 + 33), + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + 1 + 32), .RESETW (1) ) pipe_reg ( .clk (clk), .reset (reset), .enable (!stall_out), - .data_in ({alu_req_if.valid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.rd, alu_req_if.wb, alu_jal_result, is_br_op, br_op, br_dest, cmp_result}), - .data_out ({alu_commit_if.valid, alu_commit_if.wid, alu_commit_if.tmask, alu_commit_if.PC, alu_commit_if.rd, alu_commit_if.wb, alu_commit_if.data, is_br_op_r, br_op_r, branch_ctl_if.dest, cmp_result_r}) + .data_in ({alu_req_if.valid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.rd, alu_req_if.wb, alu_jal_result, is_br_op, br_taken, br_dest}), + .data_out ({alu_commit_if.valid, alu_commit_if.wid, alu_commit_if.tmask, alu_commit_if.PC, alu_commit_if.rd, alu_commit_if.wb, alu_commit_if.data, is_br_op_r, branch_ctl_if.taken, branch_ctl_if.dest}) ); assign alu_commit_if.eop = 1'b1; - - wire is_less = cmp_result_r[32]; - wire is_equal = ~(| cmp_result_r[31:0]); - - wire br_neg = `BR_NEG(br_op_r); - wire br_less = `BR_LESS(br_op_r); - wire br_static = `BR_STATIC(br_op_r); - wire br_taken = ((br_less ? is_less : is_equal) ^ br_neg) | br_static; assign branch_ctl_if.valid = alu_commit_if.valid && alu_commit_if.ready && is_br_op_r; - assign branch_ctl_if.wid = alu_commit_if.wid; - assign branch_ctl_if.taken = br_taken; + assign branch_ctl_if.wid = alu_commit_if.wid; // can accept new request? assign alu_req_if.ready = ~stall_out; diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.v index 131074ef..f08f1f16 100644 --- a/hw/rtl/VX_ibuffer.v +++ b/hw/rtl/VX_ibuffer.v @@ -11,7 +11,6 @@ module VX_ibuffer #( VX_decode_if ibuf_enq_if, // outputs - output wire [`NW_BITS-1:0] deq_wid_next, VX_decode_if ibuf_deq_if ); localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS; @@ -195,8 +194,6 @@ module VX_ibuffer #( end end - assign deq_wid_next = deq_wid_n; - assign ibuf_enq_if.ready = ~q_full[ibuf_enq_if.wid]; assign q_data_in = {ibuf_enq_if.tmask, ibuf_enq_if.PC, diff --git a/hw/rtl/VX_issue.v b/hw/rtl/VX_issue.v index 1cd122a6..026b130d 100644 --- a/hw/rtl/VX_issue.v +++ b/hw/rtl/VX_issue.v @@ -27,7 +27,6 @@ module VX_issue #( VX_gpr_req_if gpr_req_if(); VX_gpr_rsp_if gpr_rsp_if(); - wire [`NW_BITS-1:0] deq_wid_next; wire scoreboard_delay; VX_ibuffer #( @@ -37,8 +36,7 @@ module VX_issue #( .reset (reset), .freeze (1'b0), .ibuf_enq_if (decode_if), - .ibuf_deq_if (ibuf_deq_if), - .deq_wid_next (deq_wid_next) + .ibuf_deq_if (ibuf_deq_if) ); VX_scoreboard #( @@ -48,7 +46,6 @@ module VX_issue #( .reset (reset), .ibuf_deq_if (ibuf_deq_if), .writeback_if (writeback_if), - .deq_wid_next (deq_wid_next), .delay (scoreboard_delay) ); diff --git a/hw/rtl/VX_scoreboard.v b/hw/rtl/VX_scoreboard.v index 1f6b5754..19ed46b7 100644 --- a/hw/rtl/VX_scoreboard.v +++ b/hw/rtl/VX_scoreboard.v @@ -7,42 +7,34 @@ module VX_scoreboard #( input wire reset, VX_decode_if ibuf_deq_if, - VX_writeback_if writeback_if, - input wire [`NW_BITS-1:0] deq_wid_next, + VX_writeback_if writeback_if, output wire delay ); - reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n; - reg [`NUM_REGS-1:0] deq_inuse_regs; - wire [`NUM_REGS-1:0] deq_real_inuse_regs; + reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs; + wire [`NUM_REGS-1:0] deq_inuse_regs; - assign deq_real_inuse_regs = deq_inuse_regs & ibuf_deq_if.used_regs; + assign deq_inuse_regs = inuse_regs[ibuf_deq_if.wid] & ibuf_deq_if.used_regs; - assign delay = (| deq_real_inuse_regs); + assign delay = (| deq_inuse_regs); wire reserve_reg = ibuf_deq_if.valid && ibuf_deq_if.ready && (ibuf_deq_if.wb != 0); wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop; - always @(*) begin - inuse_regs_n = inuse_regs; - if (reserve_reg) begin - inuse_regs_n[ibuf_deq_if.wid][ibuf_deq_if.rd] = 1; - end - if (release_reg) begin - inuse_regs_n[writeback_if.wid][writeback_if.rd] = 0; - assert(inuse_regs[writeback_if.wid][writeback_if.rd] != 0) - else $error("*** %t: core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d", - $time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd); - end - end - always @(posedge clk) begin if (reset) begin inuse_regs <= (`NUM_WARPS*`NUM_REGS)'(0); end else begin - inuse_regs <= inuse_regs_n; - end - deq_inuse_regs <= inuse_regs_n[deq_wid_next]; + if (reserve_reg) begin + inuse_regs[ibuf_deq_if.wid][ibuf_deq_if.rd] <= 1; + end + if (release_reg) begin + inuse_regs[writeback_if.wid][writeback_if.rd] <= 0; + assert(inuse_regs[writeback_if.wid][writeback_if.rd] != 0) + else $error("*** %t: core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d", + $time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd); + end + end end `ifdef DBG_PRINT_PIPELINE @@ -50,7 +42,7 @@ module VX_scoreboard #( if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin $display("%t: core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b", $time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb, - deq_real_inuse_regs[ibuf_deq_if.rd], deq_real_inuse_regs[ibuf_deq_if.rs1], deq_real_inuse_regs[ibuf_deq_if.rs2], deq_real_inuse_regs[ibuf_deq_if.rs3]); + deq_inuse_regs[ibuf_deq_if.rd], deq_inuse_regs[ibuf_deq_if.rs1], deq_inuse_regs[ibuf_deq_if.rs2], deq_inuse_regs[ibuf_deq_if.rs3]); end end `endif @@ -63,7 +55,7 @@ module VX_scoreboard #( stall_ctr <= stall_ctr + 1; assert(stall_ctr < 10000) else $error("*** %t: core%0d-stalled: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b", $time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb, - deq_real_inuse_regs[ibuf_deq_if.rd], deq_real_inuse_regs[ibuf_deq_if.rs1], deq_real_inuse_regs[ibuf_deq_if.rs2], deq_real_inuse_regs[ibuf_deq_if.rs3]); + deq_inuse_regs[ibuf_deq_if.rd], deq_inuse_regs[ibuf_deq_if.rs1], deq_inuse_regs[ibuf_deq_if.rs2], deq_inuse_regs[ibuf_deq_if.rs3]); end else if (ibuf_deq_if.valid && ibuf_deq_if.ready) begin stall_ctr <= 0; end