minor update
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@@ -51,7 +51,9 @@ module VX_decode #(
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wire [4:0] rd = instr[11:7];
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wire [4:0] rs1 = instr[19:15];
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wire [4:0] rs2 = instr[24:20];
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`ifdef EXT_F_ENABLE
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wire [4:0] rs3 = instr[31:27];
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`endif
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wire [19:0] upper_imm = {func7, rs2, rs1, func3};
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wire [11:0] alu_imm = ((func3 == 3'h1) || (func3 == 3'h5)) ? {{7{1'b0}}, rs2} : u_12;
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