synchronous reset network optimization: only reset register when required

hw/rtl/libs/VX_bypass_buffer.v

@@ -26,7 +26,6 @@ module VX_bypass_buffer #(
         always @(posedge clk) begin
             if (reset) begin
                 buffer_valid <= 0;
-                buffer <= 0;
             end else begin            
                 if (ready_out) begin
                     buffer_valid <= 0;

hw/rtl/libs/VX_skid_buffer.v

@@ -21,10 +21,8 @@ module VX_skid_buffer #(
     
     always @(posedge clk) begin
         if (reset) begin
-            data_out_r  <= 0;
-            buffer      <= 0;
-            use_buffer  <= 0;
             valid_out_r <= 0; 
+            use_buffer  <= 0;
         end else begin             
             if (ready_out) begin
                 use_buffer <= 0;