diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v
index f6bff82f..63bd7528 100644
--- a/hw/rtl/VX_warp_sched.v
+++ b/hw/rtl/VX_warp_sched.v
@@ -200,7 +200,7 @@ module VX_warp_sched #(
     wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls);
 
     VX_lzc #(
-        .WIDTH (`NUM_WARPS)
+        .N (`NUM_WARPS)
     ) wid_select (
         .in_i    (ready_warps),
         .cnt_o   (schedule_wid),
diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v
index e36155eb..a50164a0 100644
--- a/hw/rtl/cache/VX_cache.v
+++ b/hw/rtl/cache/VX_cache.v
@@ -18,15 +18,15 @@ module VX_cache #(
     parameter WORD_SIZE                     = 4, 
 
     // Core Request Queue Size
-    parameter CREQ_SIZE                     = 2,
+    parameter CREQ_SIZE                     = 0,
     // Core Response Queue Size
     parameter CRSQ_SIZE                     = 2,
     // Miss Reserv Queue Knob
     parameter MSHR_SIZE                     = 8, 
     // Memory Response Queue Size
-    parameter MRSQ_SIZE                     = 4,
+    parameter MRSQ_SIZE                     = 0,
     // Memory Request Queue Size
-    parameter MREQ_SIZE                     = 2,
+    parameter MREQ_SIZE                     = 4,
 
     // Enable cache writeable
     parameter WRITE_ENABLE                  = 1,
diff --git a/hw/rtl/libs/VX_index_buffer.v b/hw/rtl/libs/VX_index_buffer.v
index 5bf6e514..03282b9a 100644
--- a/hw/rtl/libs/VX_index_buffer.v
+++ b/hw/rtl/libs/VX_index_buffer.v
@@ -30,7 +30,7 @@ module VX_index_buffer #(
     wire [ADDRW-1:0] free_index;
 
     VX_lzc #(
-        .WIDTH (SIZE)
+        .N (SIZE)
     ) free_slots_encoder (
         .in_i    (free_slots_n),
         .cnt_o   (free_index),
@@ -43,7 +43,6 @@ module VX_index_buffer #(
             free_slots_n[release_addr] = 1;                
         end
         if (acquire_slot)  begin
-             assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr);
              free_slots_n[write_addr_r] = 0;
         end            
     end    
@@ -58,12 +57,13 @@ module VX_index_buffer #(
             if (release_slot) begin
                 assert(0 == free_slots[release_addr]) else $error("%t: releasing invalid slot at port %d", $time, release_addr);
             end
-            if (acquire_slot || full_r) begin
-                 write_addr_r <= free_index;
+            if (acquire_slot) begin
+                assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr);                 
             end
-            free_slots <= free_slots_n;           
-            empty_r    <= (& free_slots_n);
-            full_r     <= ~free_valid;
+            write_addr_r <= free_index;
+            free_slots   <= free_slots_n;           
+            empty_r      <= (& free_slots_n);
+            full_r       <= ~free_valid;
         end        
     end
 
@@ -74,7 +74,7 @@ module VX_index_buffer #(
     ) data_table (
         .clk   (clk), 
         .wren  (acquire_slot),
-        .waddr (write_addr),
+        .waddr (write_addr_r),
         .wdata (write_data),
         .rden  (1'b1),
         .raddr (read_addr),
diff --git a/hw/rtl/libs/VX_shift_register.v b/hw/rtl/libs/VX_shift_register.v
index 33d1cf9d..e30f1f6c 100644
--- a/hw/rtl/libs/VX_shift_register.v
+++ b/hw/rtl/libs/VX_shift_register.v
@@ -13,7 +13,7 @@ module VX_shift_register_nr #(
     input wire [DATAW-1:0]          data_in,
     output wire [(NTAPS*DATAW)-1:0] data_out
 );
-    `USE_FAST_BRAM reg [DATAW-1:0] entries [DEPTH-1:0];
+    reg [DEPTH-1:0][DATAW-1:0] entries;
 
     always @(posedge clk) begin
         if (enable) begin                    
@@ -22,7 +22,7 @@ module VX_shift_register_nr #(
             entries[0] <= data_in;
         end
     end
-    
+
     for (genvar i = 0; i < NTAPS; ++i) begin
         assign data_out [i*DATAW+:DATAW] = entries [TAPS[i*DEPTHW+:DEPTHW]];
     end
@@ -42,30 +42,15 @@ module VX_shift_register_wr #(
     input wire [DATAW-1:0]          data_in,
     output wire [(NTAPS*DATAW)-1:0] data_out
 );
-    `USE_FAST_BRAM reg [DEPTH-1:0][DATAW-1:0] entries;
+    reg [DEPTH-1:0][DATAW-1:0] entries;
 
-    if (1 == DEPTH) begin
-
-        always @(posedge clk) begin
-            if (reset) begin
-                entries <= (DEPTH * DATAW)'(0);
-            end else begin
-                if (enable) begin                    
-                    entries <= data_in;
-                end
-            end
-        end
-
-    end else begin                
-        
-        always @(posedge clk) begin
-            if (reset) begin
-                entries <= (DEPTH * DATAW)'(0);
-            end else begin
-                if (enable) begin                    
-                    entries <= {entries[DEPTH-2:0], data_in};
-                end
-            end
+    always @(posedge clk) begin
+        if (reset) begin
+            entries <= '0;
+        end else if (enable) begin                    
+            for (integer i = DEPTH-1; i > 0; --i)
+                entries[i] <= entries[i-1];
+            entries[0] <= data_in;
         end
     end
 
diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile
index bd259697..7f7228a8 100644
--- a/hw/syn/quartus/pipeline/Makefile
+++ b/hw/syn/quartus/pipeline/Makefile
@@ -1,7 +1,7 @@
 PROJECT = VX_pipeline
 TOP_LEVEL_ENTITY = VX_pipeline
 SRC_FILE = VX_pipeline.v
-RTL_DIR = ../../../rtl
+RTL_DIR = ../../../../rtl
 
 FAMILY = "Arria 10"
 DEVICE = 10AX115N3F40E2SG
diff --git a/hw/syn/quartus/project.sdc b/hw/syn/quartus/project.sdc
index c45de03e..797606f7 100644
--- a/hw/syn/quartus/project.sdc
+++ b/hw/syn/quartus/project.sdc
@@ -1,4 +1,4 @@
-create_clock -name {clk} -period "220 MHz" [get_ports {clk}]
+create_clock -name {clk} -period "250 MHz" [get_ports {clk}]
 
 derive_pll_clocks -create_base_clocks
 derive_clock_uncertainty
\ No newline at end of file