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119 Commits

Author SHA1 Message Date
Hansung Kim
2f4fd11c93 Add vecadd-loop 
This is the same kernel as vecadd but repeated in a for-loop many times so that
the runtime overhead at the startup is amortized.
 2023-10-31 23:35:11 -07:00
Hansung Kim
6ffb8c37e9 [tests] Make an args.bin copy in vecadd Makefile 2023-10-07 19:15:10 -07:00
Hansung Kim
7da7a1a983 Merge remote-tracking branch 'ncastaneda02/master' 
Adds relu kernel.
 2023-10-06 13:58:25 -07:00
Nico Castaneda
5b89ff2741 added split/join to relu 2023-10-06 13:23:13 -07:00
Nico Castaneda
8296e6be0f relu test added 2023-10-06 13:20:31 -07:00
Hansung Kim
b97e94b8ed [tests] vecadd|sgemm|saxpy: save input buffers to file 2023-09-25 13:45:03 -07:00
Hansung Kim
576e7aab78 [tests] Remove -LLCFLAGS from Makefile 2023-09-25 13:28:05 -07:00
Hansung Kim
905b1877fb Add simple tid kernel that has zero arguments 2023-09-20 17:31:14 -07:00
Hansung Kim
3846d2ae59 Add annotated assembly dump for vecadd 2023-09-20 14:43:01 -07:00
Hansung Kim
c90fe56588 More doc comments 2023-09-20 14:42:56 -07:00
Hansung Kim
62ebe0312f [tests] Add comment on in-order command queue dispatch 2023-08-28 11:19:11 -07:00
Hansung Kim
c24916b5e0 [tests] Add compute-bound variant of vecadd 
This loops 1000 times over `sum += A[i] + B[i]`, making every memory op
hit at L1 cache.
 2023-07-05 21:24:53 -07:00
Hansung Kim
8caf476b1a Merge remote-tracking branch 'upstream/master' 2023-07-02 13:27:08 -07:00
Blaise Tine
b9cda8fca7 minor update 2023-05-15 20:19:14 -04:00
Hansung Kim
547216d43f [tests] reduce0, DotProduct: include LLVM_PREFIX in LD_LIBRARY_PATH 
Without this, poclcc fails with
`error while loading shared libraries: libclangCodeGen.so.10: cannot
open shared object file: No such file or directory`.
Also fix wrong kernel file name.
 2023-01-17 19:04:09 -08:00
Hansung Kim
bb4f38d000 [tests] opencl/convolution: fix linking of libsimx.so 
Fixes linker error by following suggestion of
`/usr/bin/ld: warning: libsimx.so, needed by /scratch/hansung/src/vortex/driver/simx/libvortex.so, not found (try using -rpath or -rpath-link)`.
 2023-01-17 19:04:09 -08:00
Hansung Kim
7c39cc2b5b Makefile: respect RISCV_TOOLCHAIN_PATH if already set in env 2023-01-17 19:04:03 -08:00
Blaise Tine
e1b666cb93 minor update 2022-07-14 08:55:09 -04:00
Blaise Tine
2277e3c878 minor update 2022-02-05 17:59:58 -05:00
Santosh Srivatsan
b7e5a83ba3 Merged branch xlen-parameterization into staging 2022-02-05 13:47:42 -05:00
Blaise Tine
bda77760c8 addition bug fixes 2022-02-05 09:14:35 -05:00
Blaise Tine
cf2a0a5f39 code refactoring 2022-02-04 00:07:24 -05:00
Santosh Srivatsan
212ee21b54 Updated excluded 32-bit tests 2022-02-03 22:33:47 -05:00
Santosh Srivatsan
836c777680 XLEN parameterization for simx 2022-02-03 15:19:31 -05:00
Blaise Tine
a06812f93f minor updates 2022-02-01 22:51:33 -05:00
Blaise Tine
d48f1c1c5f minor updates 2022-02-01 06:53:31 -05:00
Santosh Srivatsan
4cf596338d Minor bug fixes 2022-01-31 15:53:49 -05:00
Blaise Tine
e3e2609f7e adding unit test for vx_malloc 2022-01-30 05:57:18 -05:00
Blaise Tine
3750c672a7 Makefiles update 2022-01-30 00:26:55 -05:00
Blaise Tine
f7887d8720 refactoring device memory allocation and cleanup 2022-01-28 21:57:16 -05:00
Santosh Srivatsan
7e3a2fdb0f Modifications to allow 64-bit riscv tests to run on travis CI 2022-01-27 15:55:19 -05:00
Santosh Srivatsan
7aa93a735d Added FLEN parameterization for RV32/64 F and D instructions 2022-01-24 15:42:15 -05:00
Santosh Srivatsan
91c22a2592 Fixed some riscv-tests 2022-01-22 12:54:10 -05:00
Santosh Srivatsan
a9e3104ce1 Removed ramulator log from tests/riscv/isa 2021-12-15 17:30:12 -05:00
Santosh Srivatsan
f93303bac7 Minor update 2021-12-15 17:21:38 -05:00
Santosh Srivatsan
039f5eb733 Moved 64-bit riscv-tests to tests/riscv/isa from tests/riscv/isa64 2021-12-13 20:21:51 -05:00
Santosh Srivatsan
427146d59b Removed 64-bit runtime and regression tests 2021-12-11 17:20:40 -05:00
Santosh Srivatsan
885bb58ca9 Merged RV64IMFD extensions to master branch 2021-12-11 17:06:29 -05:00
Santosh Srivatsan
5edb9098ce Merge branch 'simx64' 2021-12-10 21:48:29 -05:00
Santosh Srivatsan
be499d6f38 Renamed simX to simx and added 64-bit riscv-tests 2021-12-10 16:56:12 -05:00
Santosh Raghav Srivatsan
bde789b320 Added support for RV32D and RV64D instructions 2021-12-10 16:30:24 -05:00
Blaise Tine
0e2de4f13a prefetch test fixes 2021-12-09 04:54:10 -05:00
Blaise Tine
fb6106267c Merge branch 'master' of https://github.com/vortexgpgpu/vortex 2021-12-09 00:00:28 -05:00
Santosh Raghav Srivatsan
e6eda67d0c Modified RV32F instructions to support 64-bit register file and added RV64F ISA extension 2021-12-06 18:55:13 -05:00
Blaise Tine
a9ec1c08a7 minor update 2021-12-06 15:44:25 -05:00
Santosh Raghav Srivatsan
30a0d34151 Fixed Makefile 2021-12-05 15:55:43 -05:00
Santosh Raghav Srivatsan
3784da0d2f riscv-tests work on simx 2021-12-01 19:41:16 -05:00
Santosh Raghav Srivatsan
f0dc04ad04 Added tests to commit. 64 bit simx still not working 2021-12-01 02:44:14 -05:00
Blaise Tine
2a7a4df342 simx directory name fix 2021-11-30 07:17:58 -05:00
Blaise Tine
41d7e6c63a cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes 2021-11-30 07:08:15 -05:00