wgulian3
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07ed4085ae
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Add power analysis Make target
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2020-03-12 13:14:50 -04:00 |
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wgulian3
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a931b588c2
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minor tweaks to appease quartus
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
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2020-03-10 12:15:30 -04:00 |
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Blaise Tine
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721d22ae86
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synthesis fixes
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2020-03-05 09:11:43 -05:00 |
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Blaise Tine
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369c2c625c
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synthesis fixes
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2020-03-05 06:58:51 -05:00 |
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wgulian3
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2c40874cc5
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Add multi-cycle compat module and use it in ALU
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2020-02-21 22:08:09 -05:00 |
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wgulian3
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de85cfd296
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fix clean build with makefile
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2020-02-19 17:33:51 -05:00 |
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wgulian3
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5dadeffac8
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fix project.tcl
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2020-02-19 14:20:58 -05:00 |
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wgulian3
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3423e3189f
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Fix e2e building issues and increase division pipeline length
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2020-02-19 01:04:48 -05:00 |
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wgulian3
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e76d05f7ce
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Fix issues quartus synthesis issues
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2020-02-18 13:24:18 -05:00 |
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wgulian3
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d727404f3b
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timing analysis tcl
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2020-01-28 04:09:00 -05:00 |
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wgulian3
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4158b29f29
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Fancier SDC file
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2020-01-28 02:20:13 -05:00 |
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wgulian3
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a6e74f589e
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Update files
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2020-01-27 20:35:45 -05:00 |
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wgulian3
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12a4136464
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quartus makefile: Support custom Quartus root location
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2020-01-24 18:42:03 -05:00 |
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wgulian3
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e9cdc6e5af
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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
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2020-01-24 06:10:24 -05:00 |
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felsabbagh3
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1b25b10644
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Full Evaluation Attempt 1
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2019-09-11 01:39:00 -04:00 |
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felsabbagh3
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3c3a443bd5
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New RF with Evaluation
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2019-09-11 01:04:23 -04:00 |
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felsabbagh3
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8d143d7739
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Quartus + GPR evaluation
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2019-09-10 20:23:01 -04:00 |
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