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2eb19e23c2c85cd2a6b68ce9cc32e8bdeccca20b
Commit Graph

351 Commits

Author SHA1 Message Date
Blaise Tine
2eb19e23c2 refactor RTL simulator 2020-03-30 01:53:34 -04:00
Blaise Tine
2d198a32c7 update 2020-03-29 23:18:26 -04:00
felsabbagh3
94cc2c10b1 Snoops shouldn't send fill requests 2020-03-29 19:16:00 -07:00
felsabbagh3
e31b2d6d7e Fixed pulling signals from different stages 2020-03-29 18:17:01 -07:00
felsabbagh3
d31116d584 Uses use_wb_valid instead of wb_req to include snoops 2020-03-29 17:59:10 -07:00
felsabbagh3
71aae3e0a9 .. 2020-03-29 17:28:57 -07:00
felsabbagh3
f96d77d75e Mismatched vs matched 2020-03-29 17:18:57 -07:00
felsabbagh3
a499bcd718 Added extra signals for debugging 2020-03-29 17:04:17 -07:00
felsabbagh3
95ee66f25a Fixed Snoop Invalidate Logic 2020-03-29 16:44:14 -07:00
felsabbagh3
73390b9f58 b/unb error 2020-03-29 16:09:48 -07:00
felsabbagh3
0a88c97485 Another reset issue... 2020-03-29 16:06:13 -07:00
felsabbagh3
b99ba2c413 Removed scheduler_empty qualifier 2020-03-29 15:24:50 -07:00
felsabbagh3
eb6e0cee43 Fixing a bug in a fix... 2020-03-29 13:52:22 -07:00
felsabbagh3
cd418a1f96 Mrvq stopping reqq popping added to avoid mrvq full deadlock 2020-03-29 13:19:06 -07:00
felsabbagh3
f43a9ad1a6 Added proper resetting to cache 2020-03-29 10:57:32 -07:00
Blaise Tine
3a23e05a88 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis 2020-03-29 05:24:48 -04:00
Blaise Tine
ce0cc44d11 update 2020-03-29 05:24:40 -04:00
felsabbagh3
efac643c66 Added Proper Handshaking to Everything and Fixed a Couple of Bugs 2020-03-29 02:11:14 -07:00
felsabbagh3
d31b607e01 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis 2020-03-28 21:43:51 -07:00
felsabbagh3
313a8e3b4b All cache bugs fixed - Handshaking 2020-03-28 21:43:02 -07:00
Blaise Tine
22be51b0c8 fixed multicore build 2020-03-28 01:40:26 -04:00
felsabbagh3
5dc9493c61 ALL tests passing - handshake 2020-03-27 21:34:49 -07:00
Blaise Tine
e80fa7f233 missing rtl changes from OPAE 2020-03-27 22:37:35 -04:00
Blaise Tine
8bb1f66220 missing rtl changes from OPAE 2020-03-27 22:37:35 -04:00
Blaise Tine
550d96a73c rtlsim driver works with Vortex! 2020-03-27 21:54:55 -04:00
Blaise Tine
e43f5c8767 rtlsim driver works with Vortex! 2020-03-27 21:54:55 -04:00
Blaise Tine
5d320a9313 fixed multicore build 2020-03-27 21:04:23 -04:00
Blaise Tine
2ed7bd3755 fixed multicore build 2020-03-27 21:04:23 -04:00
Blaise Tine
51fd8974a9 minor build fixes 2020-03-27 20:56:18 -04:00
Blaise Tine
2415199a8c minor build fixes 2020-03-27 20:56:18 -04:00
Blaise Tine
5a5c9f3981 merging changes from OPAE branch making this branch 2020-03-27 20:19:16 -04:00
Blaise Tine
9b1b8789ac merging changes from OPAE branch making this branch 2020-03-27 20:19:16 -04:00
felsabbagh3
614797e52f Migrating fpga_synthesis_temp to main 2020-03-27 13:15:23 -07:00
felsabbagh3
39516a6f98 Migrating fpga_synthesis_temp to main 2020-03-27 13:15:23 -07:00
Blaise Tine
6dc3d0d371 refactor VX_define.v 2020-03-27 13:56:16 -04:00
Blaise Tine
d54ba1e9ae refactor VX_define.v 2020-03-27 13:56:16 -04:00
Blaise Tine
3df21b6e71 fixed regression bug with Vortex.v model hanging issue 2020-03-27 13:19:11 -04:00
Blaise Tine
4eb8769423 fixed regression bug with Vortex.v model hanging issue 2020-03-27 13:19:11 -04:00
Blaise Tine
985b01cb99 adding back build_config target dependency 2020-03-27 12:41:03 -04:00
Blaise Tine
073173067f adding back build_config target dependency 2020-03-27 12:41:03 -04:00
Blaise Tine
8763adf7bc update 2020-03-26 04:19:53 -04:00
Blaise Tine
50829e522b update 2020-03-26 04:19:53 -04:00
Blaise Tine
a82dd9387d refactoring RTL simulator and Makefile 2020-03-26 04:14:36 -04:00
Blaise Tine
3252d52694 refactoring RTL simulator and Makefile 2020-03-26 04:14:36 -04:00
wgulian3
3b74f071a7 Generate define overrides based on env vars for C and Verilog. 
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
 2020-03-26 04:08:43 -04:00
wgulian3
f126a23114 Generate define overrides based on env vars for C and Verilog. 
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
 2020-03-26 04:08:43 -04:00
wgulian3
33d8c507df Remove VX_define.h and *_synth and runtime/config.h 2020-03-26 04:07:17 -04:00
wgulian3
123fb17723 Remove VX_define.h and *_synth and runtime/config.h 2020-03-26 04:07:17 -04:00
Blaise Tine
8fd742edd8 fixed Modelsim build errors 2020-03-26 03:56:44 -04:00
Blaise Tine
acafcceb94 fixed Modelsim build errors 2020-03-26 03:56:44 -04:00