Blaise Tine
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e80fa7f233
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missing rtl changes from OPAE
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2020-03-27 22:37:35 -04:00 |
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wgulian3
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83d1f54fcf
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fix shared mem ram inference
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2020-02-20 15:59:23 -05:00 |
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codetector
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ded06bcd12
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ram m10k fix
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2020-02-11 09:57:32 -05:00 |
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wgulian3
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e9cdc6e5af
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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
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2020-01-24 06:10:24 -05:00 |
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Lyons, Ethan Tyler
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52e881243e
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Warps/Threads Parameterization
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2019-11-21 01:15:54 -05:00 |
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fares
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c6d56f11c3
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Added EXEC to Warp Scheduler buffer
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2019-11-18 11:34:51 -05:00 |
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fares
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53c78b905a
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Switched to g++
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2019-11-16 12:23:59 -05:00 |
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felsabbagh3
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70651f0340
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Added a pipeline stage + fixed SM param errors
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2019-11-13 12:25:28 -05:00 |
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Lyons, Ethan Tyler
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7f7d17d176
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Shared Memory Implemented
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2019-11-13 10:06:36 -05:00 |
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felsabbagh3
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25647b46df
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Fixed SM simple
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2019-11-13 02:15:18 -05:00 |
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Lingjun Zhu
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0b30b3a35f
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Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data
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2019-10-28 15:06:23 -04:00 |
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felsabbagh3
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a8d063e9ad
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Synthesis Cleanup 1
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2019-10-28 13:43:12 -04:00 |
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felsabbagh3
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88eab9e746
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Removed dependancy on
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2019-10-27 22:30:32 -04:00 |
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felsabbagh3
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715982cca7
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Modelsim Working + Simulating + dumping - Some bugs
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2019-10-27 03:36:02 -04:00 |
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felsabbagh3
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1181af1df2
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Modelsim basic sim
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2019-10-26 00:34:57 -04:00 |
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felsabbagh3
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1645a04b1d
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Fixed SM + added def SYN
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2019-10-22 15:56:30 -04:00 |
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felsabbagh3
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9d8273afe4
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Finished Cache Integration
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2019-10-22 06:02:08 -04:00 |
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felsabbagh3
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b7af8c3f34
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Integrated Shared Memory
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2019-10-22 05:03:47 -04:00 |
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