Richard Yan
7d422cc9b0
pre-submission changes
2024-07-20 23:33:56 -07:00
Richard Yan
85213d2876
synthesizable design
2024-04-17 18:05:51 -07:00
Hansung Kim
b63333a4ec
Merge remote-tracking branch 'upstream/master' into vortex2
2024-03-07 14:45:48 -08:00
Blaise Tine
6f7a389a1f
arbiters unlock refactoring
2024-02-04 20:16:18 -08:00
Hansung Kim
48558982f7
Merge remote-tracking branch 'upstream/master' into vortex2
2024-02-01 23:35:58 -08:00
Blaise Tine
e217bc2c23
adding tracking for SFU stalls
2023-12-28 12:12:11 -08:00
Blaise Tine
c6845a4c8d
profiling timing optimization
...
minor update
minor update
minor update
2023-12-18 04:43:10 -08:00
Blaise Tine
1912f52bee
profiling bug fix
2023-12-05 04:56:46 -08:00
Hansung Kim
5825680303
[BUGFIX] Revert way_idx fix
...
The added code results in width mismatch for NUM_WAYS = 4.
2023-11-28 18:44:47 -08:00
Hansung Kim
c3c9a4b5d8
[BUGFIX] Fix wrong bitwidth of way_idx when NUM_WAYS=1
...
When NUM_WAYS=1, CLOG2(NUM_WAYS)-1 becomes -1, setting the MSB of
way_idx to a wrong value.
2023-11-28 16:05:41 -08:00
Hansung Kim
9a8020a683
Force-include gpu_pkg in VX_cache_define.vh
2023-11-28 13:55:11 -08:00
Blaise Tine
9c2916f3fc
minor update
2023-11-28 12:03:48 -08:00
Blaise Tine
d65cc61df5
minor update
2023-11-16 12:00:37 -08:00
Hansung Kim
963c2765d9
Move force-include of gpu_pkg to non-cache modules
2023-11-15 22:02:44 -08:00
Hansung Kim
20a9e6d102
Force include VX_gpu_pkg as compile order workaround
...
addResource() calls in Chisel BlackBox does not preserve order of the
files being included; the actual compile order for these files are
re-arranged to be in alphabetical order.
Therefore, while VX_gpu_pkg.sv has to be compiled before all the other
modules because it holds the top-level package definition, that order
cannot be ensured from Chisel. As a hacky workaround, simply `include
this file in some of the sv files whose name starts earlier than
VX_gpu_pkg in lexicographical order.
2023-11-14 23:00:43 -08:00
Blaise Tine
c1e168fdbe
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
minor update
minor update
minor update
minor update
minor update
cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
minor update
minor update
minor update
minor update
minor udpate
minor update
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor updates
minor updates
minor update
minor update
2023-11-10 02:47:05 -08:00
Blaise Tine
d13c5f2986
hw unit tests fixes
2023-11-05 18:51:31 -08:00
Blaise Tine
c9e6518e05
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
Blaise Tine
d47cccc157
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
Blaise Tine
d69a64c32c
minor update
2023-05-16 04:59:01 -04:00
Blaise Tine
d48f1c1c5f
minor updates
2022-02-01 06:53:31 -05:00
Blaise Tine
d7737542e4
cache uuid support
2021-12-09 20:43:22 -05:00
Blaise Tine
41d7e6c63a
cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
2021-11-30 07:08:15 -05:00
Blaise Tine
18762dffce
fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,
2021-11-24 00:00:17 -05:00
Blaise Tine
bd70afa688
cache multi-porting fix - ensure per-bank uniform rw
2021-11-14 04:44:25 -05:00
Blaise Tine
6edf38548f
text_unit merge fixes
2021-10-19 00:16:22 -04:00
Blaise Tine
bf72800676
debug tracing refactoring
2021-10-17 13:42:16 -07:00
Blaise Tine
e380ded5e1
Merge branch 'master' into graphics
2021-10-15 19:32:11 -07:00
Blaise Tine
04249c3ee9
code refactoring for Vivado compatibility
2021-09-29 04:48:53 -04:00
Blaise Tine
18c1dc2f0e
fixed interface modports
2021-09-28 02:42:04 -07:00
Blaise Tine
9f34b2944c
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
Blaise Tine
9b04f3d9d6
Updated README and synthesis scripts
2021-09-22 07:50:47 -07:00
Blaise Tine
feca2db24e
critical path optimizations
2021-09-15 04:50:45 -07:00
Blaise Tine
73d102afed
minor fix
2021-09-15 04:49:24 -07:00
Blaise Tine
142cbb8f3b
minor update
2021-09-14 09:17:08 -04:00
Blaise Tine
4e8293c3e3
cache bank pipeline optimization
2021-09-14 02:09:35 -07:00
Blaise Tine
3d7baf1640
block ram read enable fix
2021-09-14 01:45:01 -07:00
Blaise Tine
12704f9929
minor update
2021-09-11 16:47:29 -07:00
Blaise Tine
5192846c72
minor updates
2021-09-10 02:57:05 -07:00
Blaise Tine
ca46b0a0be
OUTPUT_REG => OUT_REG renaming
2021-09-09 03:05:38 -07:00
Blaise Tine
c06efbf480
minor update
2021-09-07 23:47:41 -07:00
Blaise Tine
134cbcfc5a
optimize critical path inside cache bank
2021-09-07 23:44:51 -07:00
Blaise Tine
105a24d65e
shared memory optimization
2021-09-06 23:46:36 -07:00
Blaise Tine
af1cecae07
stream arbiter update
2021-09-06 23:38:20 -07:00
Blaise Tine
3e014c8285
fmax optimizations bundles
2021-09-06 01:36:57 -07:00
Blaise Tine
b52ace5142
area optimization bundle
2021-09-05 23:35:44 -07:00
Blaise Tine
fe5112b6c1
minor updates
2021-09-05 23:05:21 -07:00
Blaise Tine
90b50277d0
cache multi-porting fixes + optimization
2021-08-29 18:33:49 -07:00
Blaise Tine
e26cfab04d
bank area optimization
2021-08-29 02:25:55 -07:00
Blaise Tine
5392395fba
minor update
2021-08-28 23:13:50 -07:00
