Hansung Kim
9ea291eea2
Merge remote-tracking branch 'origin/tensor_core' into rtl
2024-05-05 17:03:57 -07:00
joshua
5bd25985c6
i kinda forgot most of changes
2024-05-04 23:01:47 -07:00
Hansung Kim
675e8ea130
Merge branch 'tensor_core' into rtl
2024-05-01 16:18:14 -07:00
joshua
d8f9359fae
test case update
2024-03-28 13:04:02 -07:00
joshua
e16584ddd9
bleh still not work
2024-03-27 00:26:04 -07:00
joshua
beb3dce46d
integer reduction unit
2024-03-06 01:39:17 -08:00
Hansung Kim
48558982f7
Merge remote-tracking branch 'upstream/master' into vortex2
2024-02-01 23:35:58 -08:00
Blaise Tine
bd18b03cc3
minor update
2023-12-31 15:29:04 -08:00
Blaise Tine
e7f8b40d93
minor update
2023-12-31 11:46:41 -08:00
Blaise Tine
031d24e695
minor updates
2023-12-30 00:52:44 -08:00
Hansung Kim
158624bc1b
Write operand to file in matmul kernel
2023-12-30 00:28:55 -08:00
Blaise Tine
36f5dd87fe
minor update
2023-12-28 12:22:22 -08:00
Blaise Tine
e217bc2c23
adding tracking for SFU stalls
2023-12-28 12:12:11 -08:00
Blaise Tine
e04e026a14
profiling update
...
minor updates
2023-12-18 04:43:44 -08:00
Blaise Tine
c6845a4c8d
profiling timing optimization
...
minor update
minor update
minor update
2023-12-18 04:43:10 -08:00
Blaise Tine
9dc5793046
minor udpate
2023-11-27 02:21:47 -08:00
Blaise Tine
1271c9c03f
minor update
2023-11-27 02:12:12 -08:00
Blaise Tine
2f1171ca76
minor update
2023-11-27 02:04:22 -08:00
Blaise Tine
43154cf738
minor updates
2023-11-16 23:41:59 -08:00
Blaise Tine
ede5e1c311
minor update
2023-11-15 00:28:26 -08:00
Blaise Tine
61e3442ef8
adding opencl convolution benchmark
2023-11-14 22:31:30 -08:00
Blaise Tine
4e7a536918
adding tensor regression test.
2023-11-14 05:37:46 -08:00
Blaise Tine
62cdd8e993
minor update
2023-11-11 15:49:39 -08:00
Blaise Tine
c1e168fdbe
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
minor update
minor update
minor update
minor update
minor update
cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
minor update
minor update
minor update
minor update
minor udpate
minor update
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor updates
minor updates
minor update
minor update
2023-11-10 02:47:05 -08:00
Blaise Tine
b9cda8fca7
minor update
2023-05-15 20:19:14 -04:00
Blaise Tine
e1b666cb93
minor update
2022-07-14 08:55:09 -04:00
Blaise Tine
2277e3c878
minor update
2022-02-05 17:59:58 -05:00
Santosh Srivatsan
b7e5a83ba3
Merged branch xlen-parameterization into staging
2022-02-05 13:47:42 -05:00
Blaise Tine
bda77760c8
addition bug fixes
2022-02-05 09:14:35 -05:00
Blaise Tine
cf2a0a5f39
code refactoring
2022-02-04 00:07:24 -05:00
Santosh Srivatsan
212ee21b54
Updated excluded 32-bit tests
2022-02-03 22:33:47 -05:00
Santosh Srivatsan
836c777680
XLEN parameterization for simx
2022-02-03 15:19:31 -05:00
Blaise Tine
a06812f93f
minor updates
2022-02-01 22:51:33 -05:00
Blaise Tine
d48f1c1c5f
minor updates
2022-02-01 06:53:31 -05:00
Santosh Srivatsan
4cf596338d
Minor bug fixes
2022-01-31 15:53:49 -05:00
Blaise Tine
e3e2609f7e
adding unit test for vx_malloc
2022-01-30 05:57:18 -05:00
Blaise Tine
3750c672a7
Makefiles update
2022-01-30 00:26:55 -05:00
Blaise Tine
f7887d8720
refactoring device memory allocation and cleanup
2022-01-28 21:57:16 -05:00
Santosh Srivatsan
7e3a2fdb0f
Modifications to allow 64-bit riscv tests to run on travis CI
2022-01-27 15:55:19 -05:00
Santosh Srivatsan
7aa93a735d
Added FLEN parameterization for RV32/64 F and D instructions
2022-01-24 15:42:15 -05:00
Santosh Srivatsan
91c22a2592
Fixed some riscv-tests
2022-01-22 12:54:10 -05:00
Santosh Srivatsan
a9e3104ce1
Removed ramulator log from tests/riscv/isa
2021-12-15 17:30:12 -05:00
Santosh Srivatsan
f93303bac7
Minor update
2021-12-15 17:21:38 -05:00
Santosh Srivatsan
039f5eb733
Moved 64-bit riscv-tests to tests/riscv/isa from tests/riscv/isa64
2021-12-13 20:21:51 -05:00
Santosh Srivatsan
427146d59b
Removed 64-bit runtime and regression tests
2021-12-11 17:20:40 -05:00
Santosh Srivatsan
885bb58ca9
Merged RV64IMFD extensions to master branch
2021-12-11 17:06:29 -05:00
Santosh Srivatsan
5edb9098ce
Merge branch 'simx64'
2021-12-10 21:48:29 -05:00
Santosh Srivatsan
be499d6f38
Renamed simX to simx and added 64-bit riscv-tests
2021-12-10 16:56:12 -05:00
Santosh Raghav Srivatsan
bde789b320
Added support for RV32D and RV64D instructions
2021-12-10 16:30:24 -05:00
Blaise Tine
0e2de4f13a
prefetch test fixes
2021-12-09 04:54:10 -05:00
