felsabbagh3
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3b49b82c46
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GPR ASIC Working
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2019-10-29 23:20:16 -04:00 |
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felsabbagh3
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3caae2b88e
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2019-10-29 14:28:41 -04:00 |
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felsabbagh3
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4aa04e76e6
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Simulate debug
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2019-10-29 14:28:20 -04:00 |
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Lingjun Zhu
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b6558714ca
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Finished synthesis with all memory but no optimization
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2019-10-28 16:18:11 -04:00 |
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Lingjun Zhu
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0b30b3a35f
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Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data
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2019-10-28 15:06:23 -04:00 |
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felsabbagh3
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7af6575b97
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SYN=1
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2019-10-28 13:57:01 -04:00 |
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felsabbagh3
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28ee1d3c36
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Sucess Synthesis - Finding db
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2019-10-28 13:52:49 -04:00 |
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felsabbagh3
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a8d063e9ad
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Synthesis Cleanup 1
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2019-10-28 13:43:12 -04:00 |
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felsabbagh3
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88eab9e746
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Removed dependancy on
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2019-10-27 22:30:32 -04:00 |
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felsabbagh3
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1b7f28273b
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Removed -O3 from makefile
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2019-10-27 20:34:32 -04:00 |
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felsabbagh3
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0ee74bc566
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migrated 100% to modelsim
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2019-10-27 20:08:44 -04:00 |
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felsabbagh3
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715982cca7
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Modelsim Working + Simulating + dumping - Some bugs
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2019-10-27 03:36:02 -04:00 |
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felsabbagh3
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372c81d90c
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Generate VCD with ModelSim
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2019-10-26 19:35:21 -04:00 |
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felsabbagh3
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6fda88b68f
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Modelsim Makefile compile + simulate - DPI
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2019-10-26 19:01:49 -04:00 |
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felsabbagh3
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ad46194d1b
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fixed width
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2019-10-26 00:39:27 -04:00 |
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felsabbagh3
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1181af1df2
|
Modelsim basic sim
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2019-10-26 00:34:57 -04:00 |
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Elsabbagh
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9110e8367e
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modelsim
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2019-10-25 23:41:34 -04:00 |
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felsabbagh3
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667dbfbbe8
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Trying icarus
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2019-10-25 22:54:02 -04:00 |
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felsabbagh3
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820007ae80
|
NUM_REQ
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2019-10-25 13:46:31 -04:00 |
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felsabbagh3
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c85c01e082
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Parametized cache
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2019-10-25 13:36:06 -04:00 |
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felsabbagh3
|
89d0390965
|
CACHE FINALLY WORKING
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2019-10-25 04:01:23 -04:00 |
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felsabbagh3
|
01efe02e8b
|
CACHE WORKING just needs lb/sb
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2019-10-25 03:03:09 -04:00 |
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felsabbagh3
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1e648c5819
|
FIxed first circular issue
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2019-10-24 10:38:04 -04:00 |
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felsabbagh3
|
de8de00f6e
|
Finished cache not tested
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2019-10-23 19:07:26 -04:00 |
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felsabbagh3
|
6340ffcc2a
|
new cache states
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2019-10-23 15:07:14 -04:00 |
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felsabbagh3
|
1645a04b1d
|
Fixed SM + added def SYN
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2019-10-22 15:56:30 -04:00 |
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felsabbagh3
|
9d8273afe4
|
Finished Cache Integration
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2019-10-22 06:02:08 -04:00 |
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felsabbagh3
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b7af8c3f34
|
Integrated Shared Memory
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2019-10-22 05:03:47 -04:00 |
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felsabbagh3
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1bfafca896
|
Cleanup before integration
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2019-10-22 03:03:17 -04:00 |
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felsabbagh3
|
b3f464dd89
|
Barriers impl + tested
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2019-10-22 01:47:39 -04:00 |
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felsabbagh3
|
31d3d51392
|
WSPAWN imp + tested
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2019-10-21 23:35:53 -04:00 |
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felsabbagh3
|
c21e400f9f
|
Readded IPDOM stack + SPLIT/Join tested
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2019-10-21 21:26:21 -04:00 |
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felsabbagh3
|
b6375e76de
|
Readded IPDOM stack + SPLIT/Join tested
|
2019-10-21 21:24:49 -04:00 |
|
Lingjun Zhu
|
e2cd8102eb
|
Uncommented the necessary line about write_bit_mask on VX_gpr.v again, try synthesizing
|
2019-10-21 17:09:51 -04:00 |
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felsabbagh3
|
0672389edc
|
fix
|
2019-10-21 12:16:17 -04:00 |
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felsabbagh3
|
ce49e2f223
|
proper init warp scheduelr
|
2019-10-21 12:13:34 -04:00 |
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felsabbagh3
|
8050419511
|
added begin
|
2019-10-21 12:06:10 -04:00 |
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felsabbagh3
|
85004899bd
|
added reset to ws
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2019-10-21 12:03:07 -04:00 |
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felsabbagh3
|
99586279d9
|
always fix stack
|
2019-10-21 11:49:10 -04:00 |
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felsabbagh3
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292c792339
|
generic stack reset
|
2019-10-21 11:45:51 -04:00 |
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felsabbagh3
|
4bfdbb5188
|
reset posedge
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2019-10-21 11:34:12 -04:00 |
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felsabbagh3
|
49b139d512
|
fix
|
2019-10-21 11:24:45 -04:00 |
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felsabbagh3
|
121a985d12
|
Reset to Generic Register
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2019-10-21 11:21:13 -04:00 |
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felsabbagh3
|
bab1852a99
|
Added Split/Join - not tested
|
2019-10-21 03:03:15 -04:00 |
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felsabbagh3
|
84f5ccb484
|
Added CSR TID/WID reads
|
2019-10-21 02:10:05 -04:00 |
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felsabbagh3
|
797801ebae
|
CENA/CENB Modifications + Still not working
|
2019-10-19 14:52:57 -04:00 |
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felsabbagh3
|
4cae140ac1
|
Mem technology compiling but still reading all zeros
|
2019-10-18 16:45:42 -04:00 |
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felsabbagh3
|
f7d826593f
|
TMC working and tested
|
2019-10-18 16:09:06 -04:00 |
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felsabbagh3
|
f7b55427b4
|
Added ISA2 infrastructure with bugs
|
2019-10-18 05:21:32 -04:00 |
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felsabbagh3
|
629ed3f8f9
|
Before ISA2.0
|
2019-10-18 04:15:34 -04:00 |
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