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1,648 Commits 7 Branches 0 Tags
762c5da23774d23a317c2dd1cb5d10bd5718c321
Commit Graph
497 Commits
Author SHA1 Message Date
Blaise Tine 5d2437d887 refactoring cache_config 2021-05-27 14:41:46 -07:00
Blaise Tine 4c5104e96a fixed shared memory multi-tag requests bug 2021-05-26 15:03:48 -07:00
Blaise Tine d8517d4d08 minor update 2021-05-26 13:37:07 -07:00
Blaise Tine c7f85b76ed minor update 2021-05-26 13:36:10 -07:00
Blaise Tine 093008fa1e minor update 2021-05-25 09:13:32 -07:00
Blaise Tine 6388d87ec5 afu bug fix 2021-05-24 18:06:11 -07:00
Blaise Tine 244f4b0964 fixed shared memory write bug 2021-05-23 10:57:58 -07:00
Blaise Tine d3f0a77ae5 fixed databus arbiter bug 2021-05-23 10:57:02 -07:00
Blaise Tine d80e1b28a3 fixes for multi-channel memory support 2021-05-20 05:36:09 -07:00
Blaise Tine 7095a46066 minor update 2021-05-18 11:15:36 -07:00
Blaise Tine 3e88a71801 minor update 2021-05-06 08:55:46 -07:00
Blaise Tine 6107bf8247 minor fix 2021-05-04 11:05:07 -07:00
Blaise Tine 8f451aa74c minor update 2021-05-04 08:01:49 -07:00
Blaise Tine bde6a69ea0 adding support for multi-banks memory bus 2021-05-04 07:32:03 -07:00
Blaise Tine 228aee1ec7 lsu_unit pending queue bug fix 2021-05-03 12:25:44 -07:00
Blaise Tine bac53e4ae1 minor update 2021-05-02 11:05:49 -07:00
Blaise Tine 04a1c0e9eb IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr 2021-05-01 13:44:08 -07:00
Blaise Tine e40a3feefa minor update 2021-05-01 10:33:24 -07:00
Blaise Tine d504adb236 afu mem controller refactoring 2021-05-01 08:39:52 -07:00
Blaise Tine 95f057bc2e fpga build refactoring 2021-04-29 06:17:28 -07:00
Blaise Tine 64848788a1 minor update 2021-04-26 20:34:28 -07:00
Blaise Tine 8543e3a8bf code refactoring 2021-04-26 02:34:21 -07:00
Blaise Tine 8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
Blaise Tine d808aa2735 perf counters generic size 2021-04-25 21:15:24 -07:00
Blaise Tine a60361ac2d minor update 2021-04-25 21:10:54 -07:00
Blaise Tine cad21a4b92 minor update 2021-04-24 01:17:38 -04:00
Blaise Tine 4cb98a25a7 enabling 128-bit dram bus 2021-04-24 00:31:27 -04:00
Blaise Tine aff5903a22 minor ibuffer critical path optimization. 2021-04-19 20:53:13 -07:00
Blaise Tine 625689796f minor update 2021-04-04 23:42:57 -07:00
Blaise Tine 2ce6dbb495 minor update 2021-04-04 17:57:35 -07:00
Blaise Tine 5cfd6e6f82 minor updates 2021-04-04 04:04:41 -07:00
Blaise Tine d522611ee2 minor update 2021-04-03 05:07:00 -07:00
Blaise Tine d6552a8851 minor update 2021-04-03 04:24:37 -07:00
Blaise Tine f829bd3c18 minor update 2021-04-03 04:22:44 -07:00
Blaise Tine 1e2da696ce arrays logging 2021-04-02 02:20:15 -07:00
Blaise Tine a75accf6ed minor update 2021-04-01 23:31:55 -07:00
Blaise Tine 638614fd6d decode optimization 2021-04-01 19:08:15 -07:00
Blaise Tine 04a96e89c9 minor update 2021-04-01 12:34:18 -07:00
Blaise Tine a194521683 minor update 2021-03-31 02:37:16 -07:00
Blaise Tine d15e33e87f fpu dpi update 2021-03-31 02:36:34 -07:00
Blaise Tine b3167d763b minor update 2021-03-30 22:08:26 -07:00
Blaise Tine 16bef8937b adding empty to index_buffer 2021-03-30 10:15:42 -07:00
Blaise Tine b33a994f49 minor update 2021-03-29 23:51:05 -07:00
Blaise Tine fc70bb3a4a databus optimization 2021-03-29 23:48:04 -07:00
Blaise Tine 8d4e2e7f70 minor update 2021-03-22 23:04:54 -07:00
Blaise Tine 09dbeacc14 minor update 2021-03-22 23:04:35 -07:00
Blaise Tine af1bb33557 minor update 2021-03-21 16:38:53 -07:00
Blaise Tine bd40e7db70 minor update - mux reordering to reduce critical path on input data 2021-03-21 11:43:57 -07:00
Blaise Tine f7d6b71ac2 minor update 2021-03-21 11:40:54 -07:00
Blaise Tine 09194a8501 minor update 2021-03-21 11:39:33 -07:00