wu-arch/vortex
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7947df8a6c6e248584c86aeda590e8811c8d8ddd
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52 Commits

Author SHA1 Message Date
Richard Yan
7947df8a6c config change, move ucode 2024-06-12 02:15:08 -07:00
Richard Yan
a47389fc0e Merge branch 'rtl' of https://github.com/hansungk/vortex-private into rtl 2024-06-09 15:15:31 -07:00
Richard Yan
67a13410fd gate level sim changes 2024-06-09 15:15:01 -07:00
Hansung Kim
874a3bf194 Doc changes 2024-06-09 13:41:00 -07:00
Richard Yan
d624b3e50a store fencing, large smem, fix tensor core for firesim 2024-05-15 21:45:48 -07:00
Richard Yan
0dd5335851 fix merge error once again 2024-05-08 11:31:43 -07:00
Richard Yan
16dfae7d3f Merge branch 'rtl' of https://github.com/hansungk/vortex-private into rtl 2024-05-08 11:28:39 -07:00
Richard Yan
629279977e fix merge error 2024-05-08 11:28:36 -07:00
Hansung Kim
be748b109a Fix faulty merge on syn-only flags 2024-05-07 18:37:25 -07:00
Richard Yan
4aad161739 Merge branch 'rtl' of https://github.com/hansungk/vortex-private into rtl 2024-05-07 14:00:31 -07:00
Richard Yan
37616f3334 firesim modifications 2024-05-07 13:59:25 -07:00
Hansung Kim
c4b94e4f2c Wrap hardcoded configs with SYNTHESIS 2024-05-02 16:17:04 -07:00
Richard Yan
85213d2876 synthesizable design 2024-04-17 18:05:51 -07:00
Hansung Kim
eb63767051 Don't hardcode SIMULATION 2024-02-01 23:58:06 -08:00
Hansung Kim
48558982f7 Merge remote-tracking branch 'upstream/master' into vortex2 2024-02-01 23:35:58 -08:00
Blaise Tine
38b92ad592 - using SV_DPI defines to disable DPI in synthesis-based simulations 
- fixed Intel ASE run script: run_ase.sh
 2024-01-28 00:22:21 -08:00
Hansung Kim
c9d1275f0e Define SIMULATION under VERILATOR 2024-01-25 23:23:34 -08:00
Hansung Kim
d2d7ee61bb Define SIMULATION for VCS in VX_platform.vh 2023-11-15 19:14:58 -08:00
Hansung Kim
512fc0da1c Copy VX_platform macros for VCS from VERILATOR 2023-11-15 00:20:18 -08:00
Blaise Tine
d47cccc157 Vortex 2.0 changes: 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
 2023-10-19 20:51:22 -07:00
Blaise Tine
bf72800676 debug tracing refactoring 2021-10-17 13:42:16 -07:00
Blaise Tine
e380ded5e1 Merge branch 'master' into graphics 2021-10-15 19:32:11 -07:00
Blaise Tine
668cfb5da4 text_addr optimization 2021-10-14 13:00:17 -07:00
Blaise Tine
8e82ee00a0 minor update 2021-09-29 09:32:21 -07:00
Blaise Tine
a45261b530 code refactoring for Vivado compatibility 2021-09-29 03:24:17 -04:00
Blaise Tine
9f34b2944c code refactoring for Vivado, sv2v, and yosys compatibility 2021-09-27 08:55:10 -04:00
Blaise Tine
a46c32ed4b Adding Vortex Yosys build support 2021-09-08 23:04:33 -04:00
Blaise Tine
2a27bfbfd5 LKG Build (reset network update -fmax=236 mhz 4c) 2021-08-23 01:59:22 -07:00
Blaise Tine
c2b3aaa7d1 enabling delayed tracing 2021-08-12 20:05:43 -07:00
Blaise Tine
43ad188ccb texture unit critical path optimization 2021-08-05 02:47:26 -07:00
Blaise Tine
7b8fe11e6a unused variables refactoring 2021-08-05 01:46:26 -07:00
Blaise Tine
bb1ceffadd rebase master update 2021-07-30 21:03:14 -07:00
Blaise Tine
7d01be367c reset network refactoring 2021-07-15 11:34:55 -07:00
Blaise Tine
d504adb236 afu mem controller refactoring 2021-05-01 08:39:52 -07:00
Blaise Tine
1e2da696ce arrays logging 2021-04-02 02:20:15 -07:00
Blaise Tine
062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
Blaise Tine
3c37db877a cache specialization for in-order DRAM reponses 2021-02-13 20:23:29 -08:00
Blaise Tine
8775f63ec4 lkg build rollout with 16cores optimization on arria10 2021-01-24 16:49:22 -08:00
Blaise Tine
2d69ca5d67 scratchpad optimization for stack access using custom bank offset aligned to stack size 2021-01-02 16:00:00 -05:00
Blaise Tine
4bbd7bf408 performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies, 2020-12-19 02:45:06 -08:00
Blaise Tine
725322807e fixed DRAM response backpressure inside Cache 2020-11-10 05:24:57 -08:00
Blaise Tine
3fe31fc337 fixed afu to cpu mempcy hang 2020-10-28 14:19:13 -07:00
Blaise Tine
43ae82e788 vlsim fix, verilator fst trace, use ram optimization 2020-10-25 16:40:50 -07:00
Blaise Tine
7529f72c5d fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags 2020-10-20 05:32:55 -07:00
Blaise Tine
32da50816f scope refactoring: adding modules definitions to VCD trace 2020-10-12 23:26:02 -04:00
Blaise Tine
309dd48fc6 scope bug fixes 2020-10-06 03:59:27 -04:00
Blaise Tine
4e1007e5b2 scope refactoring 2020-10-03 18:53:21 -04:00
Blaise Tine
0a0b28aac0 minor update - 206-214 mhz 2020-08-29 05:14:08 -07:00
Blaise Tine
0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
Blaise Tine
6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00