Blaise Tine
|
65c1078158
|
minor update
|
2021-07-01 06:51:36 -04:00 |
|
Blaise Tine
|
93fee18d59
|
minor update
|
2021-07-01 02:59:44 -07:00 |
|
Blaise Tine
|
e8c01e18d8
|
regression fixes
|
2021-06-29 04:32:32 -04:00 |
|
Blaise Tine
|
d684a2e632
|
application exit error handing
|
2021-06-29 02:04:07 -04:00 |
|
Blaise Tine
|
7e0dc81cee
|
minor update
|
2021-06-23 04:19:13 -07:00 |
|
Blaise Tine
|
2372067817
|
minor update
|
2021-06-22 09:30:36 -07:00 |
|
Blaise Tine
|
6213b1a910
|
vortex runtime console out implementation
|
2021-06-15 04:01:44 -04:00 |
|
Blaise Tine
|
03406c0a3f
|
project tests refactoring
|
2021-06-13 17:42:04 -07:00 |
|
Blaise Tine
|
3cc1190cd7
|
CSRs I/O refactoring
|
2021-06-11 03:08:07 -07:00 |
|
Blaise Tine
|
a46d6cb606
|
ebreak workaround for RISC-V tests
|
2021-06-10 19:55:33 -07:00 |
|
Blaise Tine
|
3071fb7a29
|
adding support for non-cacheable memory addressing
|
2021-06-06 13:35:55 -07:00 |
|
Blaise Tine
|
df7d91d690
|
more testing
|
2021-05-26 15:29:39 -07:00 |
|
Blaise Tine
|
b3e54e66f8
|
fixed compiler warnings
|
2021-05-23 10:54:06 -07:00 |
|
Blaise Tine
|
269c06f7ea
|
minor update
|
2021-04-29 23:58:45 -07:00 |
|
Blaise Tine
|
95f057bc2e
|
fpga build refactoring
|
2021-04-29 06:17:28 -07:00 |
|
Blaise Tine
|
8543e3a8bf
|
code refactoring
|
2021-04-26 02:34:21 -07:00 |
|
Blaise Tine
|
8410c49f53
|
code refactoring: DRAM => MEM renaming
|
2021-04-26 00:58:48 -07:00 |
|
Blaise Tine
|
4cb98a25a7
|
enabling 128-bit dram bus
|
2021-04-24 00:31:27 -04:00 |
|
Blaise Tine
|
062d02ddce
|
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
|
2021-03-04 20:51:03 -08:00 |
|
Blaise Tine
|
700f9eea19
|
moving MUL unit into ALU unit
|
2021-02-23 13:49:02 -08:00 |
|
Blaise Tine
|
5419859281
|
fcvt fix
|
2021-01-25 02:22:00 -08:00 |
|
Blaise Tine
|
ce9ef840d6
|
minor updates
|
2021-01-18 04:22:40 -08:00 |
|
Blaise Tine
|
ac2242b51f
|
minor update
|
2021-01-07 00:18:10 -08:00 |
|
Blaise Tine
|
146c285aa0
|
minor update
|
2021-01-06 19:59:04 -08:00 |
|
Blaise Tine
|
2b8435471a
|
speeding up simulation using dedicated full dpi-based FPU core
|
2021-01-06 18:44:06 -08:00 |
|
Blaise Tine
|
39bff921be
|
cache bug fixes
|
2021-01-05 05:04:49 -08:00 |
|
Blaise Tine
|
762b8e2e3e
|
fixed cache mshr critical path
|
2021-01-04 12:49:40 -05:00 |
|
Blaise Tine
|
4bc3b537bd
|
fixed reset fan-out
|
2021-01-03 20:06:36 -08:00 |
|
Blaise Tine
|
4815ab099c
|
using single-port block ram for cache tags, restoring core reset signal
|
2021-01-02 19:53:41 -08:00 |
|
Blaise Tine
|
703a861fe9
|
added support for write-through cache, removed cache snooping support
|
2020-12-23 23:51:02 -08:00 |
|
Blaise Tine
|
d956e268b9
|
adding new performance counters (banks utilization and DRAM bus utilization)
|
2020-12-22 12:33:45 -08:00 |
|
Blaise Tine
|
4bbd7bf408
|
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
|
2020-12-19 02:45:06 -08:00 |
|
Blaise Tine
|
dada72f830
|
minor update
|
2020-12-06 15:28:58 -08:00 |
|
Blaise Tine
|
b7a724410b
|
update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache)
|
2020-12-03 07:30:19 -08:00 |
|
Blaise Tine
|
97739e9dcf
|
RAM blocks inference fixes
|
2020-11-30 14:02:47 -08:00 |
|
Blaise Tine
|
b85391389b
|
rename MSRQ to MSHR
|
2020-11-28 17:32:00 -05:00 |
|
Blaise Tine
|
00d7473268
|
build warnings clean
|
2020-11-28 14:59:13 -05:00 |
|
Blaise Tine
|
457f831435
|
fixed scoreboard stall
|
2020-11-28 03:14:20 -05:00 |
|
Blaise Tine
|
461be0880d
|
fixed FPU-CSR data dependence
|
2020-11-25 09:05:38 -08:00 |
|
Blaise Tine
|
664ce28426
|
minor update
|
2020-11-23 12:21:39 -08:00 |
|
Blaise Tine
|
2d4fef6dd6
|
fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles
|
2020-11-23 11:59:40 -08:00 |
|
Blaise Tine
|
1795980a52
|
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
|
2020-11-21 09:47:56 -08:00 |
|
Blaise Tine
|
e946d976e7
|
constant integration updates
|
2020-11-15 08:44:57 -08:00 |
|
Blaise Tine
|
5d58bf3d11
|
fixed l3cache hang using memory arbiter in afu
|
2020-11-15 06:36:32 -08:00 |
|
Blaise Tine
|
203a184008
|
fixed bank_core_req_abr critical path
|
2020-11-08 18:25:32 -08:00 |
|
Blaise Tine
|
5be1d85648
|
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
|
2020-11-02 01:50:12 -08:00 |
|
Blaise Tine
|
4bd5ee2673
|
fixed rtlsim regression
|
2020-10-26 12:59:58 -04:00 |
|
Blaise Tine
|
43ae82e788
|
vlsim fix, verilator fst trace, use ram optimization
|
2020-10-25 16:40:50 -07:00 |
|
Blaise Tine
|
4e1007e5b2
|
scope refactoring
|
2020-10-03 18:53:21 -04:00 |
|
Blaise Tine
|
990b1585f1
|
CI script updates
|
2020-09-20 01:27:34 -04:00 |
|