15 Commits

Include renames

Author	SHA1	Message	Date
Blaise Tine	369c2c625c	synthesis fixes	2020-03-05 06:58:51 -05:00
felsabbagh3	25b6dbdfa8	Fixed incorrect valid and'ing in execute	2020-03-03 20:57:20 -08:00
wgulian3	8318aff69f	Support exec multi-cycle for div/mul	2020-02-13 13:17:46 -05:00
wgulian3	e9cdc6e5af	SystemVerilog tweaks to appease Quartus and make Quartus synthesis work	2020-01-24 06:10:24 -05:00
Lyons, Ethan TylerandGitHub Enterprise	509850192c	Warps/Threads Parameterization	2019-11-21 01:14:50 -05:00
fares	c6d56f11c3	Added EXEC to Warp Scheduler buffer	2019-11-18 11:34:51 -05:00
felsabbagh3	58a9140f08	Before evict_wb_old removal	2019-11-07 13:27:38 -05:00
felsabbagh3	bbb2373919	Intrinsics: tests for TMC+Control Divergence	2019-11-01 21:53:37 -04:00
felsabbagh3	1181af1df2	Modelsim basic sim	2019-10-26 00:34:57 -04:00
felsabbagh3	1bfafca896	Cleanup before integration	2019-10-22 03:03:17 -04:00
felsabbagh3	b6375e76de	Readded IPDOM stack + SPLIT/Join tested	2019-10-21 21:24:49 -04:00
felsabbagh3	84f5ccb484	Added CSR TID/WID reads	2019-10-21 02:10:05 -04:00
felsabbagh3	559c64cb36	Cleanup	2019-10-18 02:20:38 -04:00
felsabbagh3	505bbc20c8	Removed FWD	2019-10-18 02:01:39 -04:00
felsabbagh3	6779d0fade	Instruction Multiplex LSU/EXU 1 cycle DONE	2019-10-17 22:29:21 -04:00