15 Commits

Include renames

Author	SHA1	Message	Date
wgulian3	e9cdc6e5af	SystemVerilog tweaks to appease Quartus and make Quartus synthesis work	2020-01-24 06:10:24 -05:00
Lyons, Ethan TylerandGitHub Enterprise	52e881243e	Warps/Threads Parameterization	2019-11-21 01:15:54 -05:00
fares	c6d56f11c3	Added EXEC to Warp Scheduler buffer	2019-11-18 11:34:51 -05:00
fares	53c78b905a	Switched to g++	2019-11-16 12:23:59 -05:00
felsabbagh3	70651f0340	Added a pipeline stage + fixed SM param errors	2019-11-13 12:25:28 -05:00
Lyons, Ethan TylerandGitHub Enterprise	7f7d17d176	Shared Memory Implemented	2019-11-13 10:06:36 -05:00
felsabbagh3	25647b46df	Fixed SM simple	2019-11-13 02:15:18 -05:00
Lingjun Zhu	0b30b3a35f	Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data	2019-10-28 15:06:23 -04:00
felsabbagh3	a8d063e9ad	Synthesis Cleanup 1	2019-10-28 13:43:12 -04:00
felsabbagh3	88eab9e746	Removed dependancy on	2019-10-27 22:30:32 -04:00
felsabbagh3	715982cca7	Modelsim Working + Simulating + dumping - Some bugs	2019-10-27 03:36:02 -04:00
felsabbagh3	1181af1df2	Modelsim basic sim	2019-10-26 00:34:57 -04:00
felsabbagh3	1645a04b1d	Fixed SM + added def SYN	2019-10-22 15:56:30 -04:00
felsabbagh3	9d8273afe4	Finished Cache Integration	2019-10-22 06:02:08 -04:00
felsabbagh3	b7af8c3f34	Integrated Shared Memory	2019-10-22 05:03:47 -04:00