felsabbagh3
|
b216da5a6a
|
ram stdint + Quartus Files
|
2019-06-11 21:13:30 -07:00 |
|
felsabbagh3
|
d7afef04a9
|
Sim Work miss
|
2019-05-18 23:42:55 +04:00 |
|
felsabbagh3
|
48468ed26a
|
Proper SIMT with fine-grain scheduler implemented
|
2019-05-10 00:49:54 -07:00 |
|
felsabbagh3
|
719ed25213
|
Cleanup
|
2019-03-31 16:30:37 -04:00 |
|
felsabbagh3
|
8c2ae97510
|
1 WARP 8 THREADS TESTED + FULLY WORKING
|
2019-03-31 05:21:00 -04:00 |
|
felsabbagh3
|
c83ef94d02
|
1 WARP 2 THREADS WORKING
|
2019-03-31 05:02:55 -04:00 |
|
felsabbagh3
|
a3a3b21de7
|
Using verilog For-loops + Passing all tests
|
2019-03-30 22:09:03 -04:00 |
|
felsabbagh3
|
99a0792a0c
|
Passing all tests with 2 threads
|
2019-03-30 03:54:20 -04:00 |
|
felsabbagh3
|
d02c3d25b7
|
sync
|
2019-03-27 13:52:13 -04:00 |
|
felsabbagh3
|
68f3ba84e5
|
Added HW threads - Infinite loop + fixed valid
|
2019-03-27 03:53:59 -04:00 |
|
felsabbagh3
|
9b42e79dcf
|
Added HW threads - Infinite loop
|
2019-03-27 03:44:14 -04:00 |
|
felsabbagh3
|
cc0fb0eece
|
better use of valid signal
|
2019-03-27 00:07:59 -04:00 |
|
felsabbagh3
|
01d142c6e6
|
rtl passing all tests
|
2019-03-22 02:44:53 -04:00 |
|
felsabbagh3
|
656475b3b3
|
Passing Most tests
|
2019-03-21 23:47:48 -04:00 |
|