6 Commits

Author	SHA1	Message	Date
felsabbagh3	7b4b44e5ab	Fixed DRAM random latency simulator	2020-03-31 20:33:45 -07:00
Blaise Tine	bca5ac5e7f	enable rtl sim dram stalls	2020-03-31 02:41:14 -04:00
Blaise Tine	e92c4b6774	enable rtl sim dram stalls	2020-03-31 02:38:18 -04:00
felsabbagh3	66a837b0df	SOC only 2 errors	2020-03-30 21:28:40 -07:00
Blaise Tine	f6eb5dfbae	refactor RTL sim, added DRAM stalls support	2020-03-30 04:13:19 -04:00
Blaise Tine	2eb19e23c2	refactor RTL simulator	2020-03-30 01:53:34 -04:00