Blaise Tine
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f6eb5dfbae
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refactor RTL sim, added DRAM stalls support
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2020-03-30 04:13:19 -04:00 |
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Blaise Tine
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2eb19e23c2
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refactor RTL simulator
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2020-03-30 01:53:34 -04:00 |
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felsabbagh3
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313a8e3b4b
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All cache bugs fixed - Handshaking
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2020-03-28 21:43:02 -07:00 |
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Blaise Tine
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e80fa7f233
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missing rtl changes from OPAE
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2020-03-27 22:37:35 -04:00 |
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Blaise Tine
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a82dd9387d
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refactoring RTL simulator and Makefile
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2020-03-26 04:14:36 -04:00 |
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felsabbagh3
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4e6de0dc38
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Fixed most of the cache issues, mat_add left
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2020-03-22 15:59:45 -07:00 |
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wgulian3
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902aa685b1
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Add threaded -O3 build mode
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2020-03-21 17:23:40 -04:00 |
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felsabbagh3
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b038bdb491
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New Cache Design Passing All Tests
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2020-03-04 23:24:32 -08:00 |
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felsabbagh3
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6bf25b5b78
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+Added icache stage -- 3rd case of AUIPC os broken?
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2020-03-01 18:01:02 -08:00 |
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wgulian3
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4184980188
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verilator: run all riscv tests
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2020-02-13 13:50:57 -05:00 |
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wgulian3
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e662ef4134
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Fix verilator
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2020-02-13 13:42:43 -05:00 |
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felsabbagh3
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01efe02e8b
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CACHE WORKING just needs lb/sb
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2019-10-25 03:03:09 -04:00 |
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felsabbagh3
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1e648c5819
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FIxed first circular issue
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2019-10-24 10:38:04 -04:00 |
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felsabbagh3
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6b729fd2ea
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minor
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2019-10-18 01:46:38 -04:00 |
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