12 Commits

Author	SHA1	Message	Date
Blaise Tine	c1e168fdbe	Vortex 2.0 changes: ... + Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update	2023-11-10 02:47:05 -08:00
Blaise Tine	b995843a5b	cocogfx fixes and refactoring	2021-11-25 13:58:09 -05:00
Blaise Tine	54bddeee9c	simulation framework refactoring	2021-10-09 10:20:42 -04:00
Blaise Tine	03406c0a3f	project tests refactoring	2021-06-13 17:42:04 -07:00
Xandy Liu	1595ff08e2	PERF pipeline stalls and cache	2020-12-08 01:14:41 -05:00
Blaise Tine	d319ae3b97	minor rupdate	2020-10-26 05:27:10 -04:00
Blaise Tine	09b1c0eea7	minor update	2020-10-26 02:02:05 -07:00
Blaise Tine	f6f95e0c46	mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL	2020-09-19 14:45:42 -04:00
MalikBurton	b7da1dbcb8	Reordered make list to make runtime go last	2020-08-15 13:05:15 -04:00
Blaise Tine	c9755a0c48	lkg build with pipeline + FPU fixes	2020-07-31 09:29:44 -04:00
Blaise Tine	9ae38433fb	VX_pipeline refactoring + logic analyzer	2020-06-06 01:52:44 -04:00
Blaise Tine	106d707024	verilator suppor for opae (partial)	2020-06-03 06:22:49 -04:00