Blaise Tine
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c7a81d1493
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adding sockets support to simx and cache subsystem refactoring
minor update
minor update
minor updates
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2023-12-20 15:16:12 -08:00 |
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Blaise Tine
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e04e026a14
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profiling update
minor updates
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2023-12-18 04:43:44 -08:00 |
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Blaise Tine
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4b68235389
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fixed simx dispatcher bug
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2023-11-27 04:50:55 -08:00 |
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Blaise Tine
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d47cccc157
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Vortex 2.0 changes:
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
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2023-10-19 20:51:22 -07:00 |
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Santosh Srivatsan
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b7e5a83ba3
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Merged branch xlen-parameterization into staging
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2022-02-05 13:47:42 -05:00 |
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Blaise Tine
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5fbace9fa0
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fixed several bugs and refactor memory access
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2022-02-04 17:50:19 -05:00 |
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Blaise Tine
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cf2a0a5f39
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code refactoring
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2022-02-04 00:07:24 -05:00 |
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Santosh Srivatsan
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836c777680
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XLEN parameterization for simx
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2022-02-03 15:19:31 -05:00 |
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Blaise Tine
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a06812f93f
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minor updates
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2022-02-01 22:51:33 -05:00 |
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Santosh Srivatsan
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ad92c09f5b
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Changed all instances of DWord to XWord and DWordI to XWordI. Added XLEN parameterization to the simx Makefile
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2022-01-22 13:47:44 -05:00 |
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Blaise Tine
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29df0da8b5
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minor warning fixes
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2022-01-10 20:33:37 -05:00 |
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Santosh Srivatsan
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4abfca4cb2
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Replaced all instanced of DoubleWord to DWord and DoubleWordI to DWordI
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2021-12-13 19:55:02 -05:00 |
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Santosh Srivatsan
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885bb58ca9
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Merged RV64IMFD extensions to master branch
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2021-12-11 17:06:29 -05:00 |
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Blaise Tine
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5825b7c15a
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dram simulator fix
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2021-12-07 22:44:06 -05:00 |
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Blaise Tine
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b741807f8c
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using ramulator dram simulator
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2021-12-06 01:22:45 -05:00 |
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Blaise Tine
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092ff42ab4
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simx multicore fix
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2021-12-01 00:12:16 -05:00 |
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Blaise Tine
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2a7a4df342
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simx directory name fix
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2021-11-30 07:17:58 -05:00 |
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