Santosh Raghav Srivatsan
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dd12d3f848
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vortex tutorial assignment 5 solution
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2021-10-15 18:25:54 -04:00 |
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Blaise Tine
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a45261b530
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code refactoring for Vivado compatibility
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2021-09-29 03:24:17 -04:00 |
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Blaise Tine
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9f34b2944c
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code refactoring for Vivado, sv2v, and yosys compatibility
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2021-09-27 08:55:10 -04:00 |
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Blaise Tine
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81bee3ac45
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-09-08 02:27:53 -07:00 |
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Blaise Tine
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aeeb3ca616
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ALU unit critical path optimization
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2021-09-07 23:54:10 -07:00 |
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Blaise Tine
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d3c3d551ff
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-08-31 03:36:37 -04:00 |
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Blaise Tine
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c162ce526f
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adding predicate instruction
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2021-08-31 03:23:59 -04:00 |
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Blaise Tine
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53c8cddccf
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LKG build - minor update
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2021-08-30 10:25:52 -07:00 |
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Blaise Tine
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a801a16062
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instruction decode refactoring fixing naming collision
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2021-08-29 20:07:34 -07:00 |
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Blaise Tine
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90b50277d0
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cache multi-porting fixes + optimization
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2021-08-29 18:33:49 -07:00 |
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Blaise Tine
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12b8b4af24
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minor updates
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2021-08-28 15:21:40 -07:00 |
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Blaise Tine
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7202bdf977
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minor update
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2021-08-12 01:51:46 -07:00 |
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Blaise Tine
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0319283ea7
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minor update
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2021-07-20 21:42:22 -07:00 |
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Blaise Tine
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201aa2c6ad
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minor udpate
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2021-06-28 09:14:06 -07:00 |
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Blaise Tine
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c6afc35989
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adding data fence support
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2021-06-28 06:12:18 -07:00 |
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Blaise Tine
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6ae2f5199d
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decode optimization
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2021-06-28 05:06:30 -07:00 |
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Blaise Tine
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41069ba188
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non-cacheable memory address fixes
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2021-06-06 20:54:36 -07:00 |
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Blaise Tine
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3071fb7a29
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adding support for non-cacheable memory addressing
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2021-06-06 13:35:55 -07:00 |
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Blaise Tine
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95f057bc2e
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fpga build refactoring
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2021-04-29 06:17:28 -07:00 |
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Blaise Tine
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8543e3a8bf
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code refactoring
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2021-04-26 02:34:21 -07:00 |
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Blaise Tine
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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Blaise Tine
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d808aa2735
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perf counters generic size
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2021-04-25 21:15:24 -07:00 |
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Blaise Tine
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8a9a67aa5a
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minor update
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2021-02-27 21:54:55 -08:00 |
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Blaise Tine
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f5a17bd1a9
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decode optimization and refactoring
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2021-02-27 18:21:41 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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ab63ac9e5d
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cache request interfaces update
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2021-02-10 20:55:04 -08:00 |
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Blaise Tine
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fcbf57b66a
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specialized shared memory module
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2021-01-16 04:41:58 -08:00 |
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Blaise Tine
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7c4823e65c
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fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
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2021-01-11 23:55:09 -08:00 |
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Blaise Tine
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06945533cf
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fixed l2/l3 caches related bugs
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2021-01-09 16:32:55 -08:00 |
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Blaise Tine
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9cef1aae04
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cache fill response address is the mshr's top address, no need to store it
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2021-01-03 00:57:24 -05:00 |
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Blaise Tine
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2d69ca5d67
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scratchpad optimization for stack access using custom bank offset aligned to stack size
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2021-01-02 16:00:00 -05:00 |
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Blaise Tine
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30d950ada2
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vx_spawn_warps redesign using opencl's style scheduler
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2021-01-01 14:13:48 -05:00 |
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Blaise Tine
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138db29310
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-12-31 22:40:34 -05:00 |
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Blaise Tine
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e4a00dd0d9
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fixed loader script stack setup
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2020-12-31 22:37:20 -05:00 |
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Blaise Tine
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abe32ed553
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cache optimization - moved read requests to stage1 and eliminating stage3
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2020-12-31 07:40:58 -08:00 |
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Blaise Tine
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703a861fe9
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added support for write-through cache, removed cache snooping support
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2020-12-23 23:51:02 -08:00 |
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Blaise Tine
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d5438fd591
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merging perf counters
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2020-12-08 21:02:39 -08:00 |
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Blaise Tine
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268ad15098
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minor update
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2020-12-06 22:55:17 -08:00 |
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Blaise Tine
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1332970636
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refactoring cores clustering
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2020-12-06 14:42:12 -08:00 |
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Blaise Tine
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b2652527bb
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data/dram bus refactoring
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2020-12-06 03:37:22 -08:00 |
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Blaise Tine
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f3b1069ce8
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adding stream arbiter
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2020-12-03 06:40:23 -08:00 |
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Blaise Tine
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20f22c7446
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scope minor fix
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2020-11-22 11:51:46 -08:00 |
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Blaise Tine
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1795980a52
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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
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2020-11-21 09:47:56 -08:00 |
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Blaise Tine
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5d58bf3d11
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fixed l3cache hang using memory arbiter in afu
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2020-11-15 06:36:32 -08:00 |
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Blaise Tine
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10505caae1
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refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2
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2020-11-08 01:31:46 -08:00 |
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Blaise Tine
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43ae82e788
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vlsim fix, verilator fst trace, use ram optimization
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2020-10-25 16:40:50 -07:00 |
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Blaise Tine
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4e1007e5b2
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scope refactoring
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2020-10-03 18:53:21 -04:00 |
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Blaise Tine
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42e3b6c45d
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fixed lmp_mult parameters, ram init filepath
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2020-09-04 07:51:46 -07:00 |
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Blaise Tine
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df711986bc
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FPU DPI fallback
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2020-08-31 09:19:55 -04:00 |
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Blaise Tine
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0a0b28aac0
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minor update - 206-214 mhz
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2020-08-29 05:14:08 -07:00 |
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