13 Commits

Include renames

Author	SHA1	Message	Date
Santosh Raghav Srivatsan	e6eda67d0c	Modified RV32F instructions to support 64-bit register file and added RV64F ISA extension	2021-12-06 18:55:13 -05:00
Santosh Raghav Srivatsan	3784da0d2f	riscv-tests work on simx	2021-12-01 19:41:16 -05:00
Santosh Raghav Srivatsan	f0dc04ad04	Added tests to commit. 64 bit simx still not working	2021-12-01 02:44:14 -05:00
Santosh Raghav Srivatsan	64d47f3637	Added support for RV64I instructions	2021-11-27 12:33:30 -05:00
Santosh Raghav Srivatsan	d1892bd6ec	Added support for a few RV64I instructions	2021-11-11 13:35:14 -05:00
Santosh Raghav Srivatsan	9cd8dec397	Extended register file to 64 bits	2021-11-08 17:54:16 -05:00
Blaise Tine	e248f744d5	Merge branch 'master' of https://github.com/vortexgpgpu/vortex	2021-10-19 03:07:13 -04:00
Santosh Raghav Srivatsan	dd12d3f848	vortex tutorial assignment 5 solution	2021-10-15 18:25:54 -04:00
Blaise Tine	4a4498cd53	minor update	2021-10-11 18:32:17 -04:00
Blaise Tine	7102ca5394	minor update	2021-10-10 20:00:56 -04:00
Blaise Tine	b8682f56ac	softfloat library integration	2021-10-10 13:20:50 -07:00
Blaise Tine	28e26f3130	minor update	2021-10-09 13:19:46 -07:00
Blaise Tine	54bddeee9c	simulation framework refactoring	2021-10-09 10:20:42 -04:00