#include #include #include #include #include #include #include #include "processor.h" #include "constants.h" #include #include "args.h" using namespace vortex; int main(int argc, char **argv) { int exitcode = 0; std::string archStr("rv32imf"); std::string imgFileName; int num_cores(NUM_CORES * NUM_CLUSTERS); int num_warps(NUM_WARPS); int num_threads(NUM_THREADS); bool showHelp(false); bool showStats(false); bool riscv_test(false); /* Read the command line arguments. */ CommandLineArgFlag fh("-h", "--help", "", showHelp); CommandLineArgSetter fa("-a", "--arch", "", archStr); CommandLineArgSetter fi("-i", "--image", "", imgFileName); CommandLineArgSetter fc("-c", "--cores", "", num_cores); CommandLineArgSetter fw("-w", "--warps", "", num_warps); CommandLineArgSetter ft("-t", "--threads", "", num_threads); CommandLineArgFlag fr("-r", "--riscv", "", riscv_test); CommandLineArgFlag fs("-s", "--stats", "", showStats); CommandLineArg::readArgs(argc - 1, argv + 1); if (showHelp || imgFileName.empty()) { std::cout << "Vortex emulator command line arguments:\n" " -i, --image Program RAM image\n" " -c, --cores Number of cores\n" " -w, --warps Number of warps\n" " -t, --threads Number of threads\n" " -a, --arch Architecture string\n" " -r, --riscv riscv test\n" " -s, --stats Print stats on exit.\n"; return 0; } std::cout << "Running " << imgFileName << "..." << std::endl; if (!SimPlatform::instance().initialize()) return -1; { RAM ram(RAM_PAGE_SIZE); { std::string program_ext(fileExtension(imgFileName.c_str())); if (program_ext == "bin") { ram.loadBinImage(imgFileName.c_str(), STARTUP_ADDR); } else if (program_ext == "hex") { ram.loadHexImage(imgFileName.c_str()); } else { std::cout << "*** error: only *.bin or *.hex images supported." << std::endl; return -1; } } ArchDef arch(archStr, num_cores, num_warps, num_threads); auto processor = Processor::Create(arch); processor->attach_ram(&ram); // setup memory simulator auto memsim = MemSim::Create(MemSim::Config{ DRAM_CHANNELS, arch.num_cores() }); processor->MemReqPort.bind(&memsim->MemReqPort); memsim->MemRspPort.bind(&processor->MemRspPort); // run simulation for (;;) { SimPlatform::instance().step(); if (processor->check_exit(&exitcode)) break; }; } SimPlatform::instance().finalize(); if (riscv_test) { if (1 == exitcode) { std::cout << "Passed." << std::endl; exitcode = 0; } else { std::cout << "Failed." << std::endl; } } else { if (exitcode != 0) { std::cout << "*** error: exitcode=" << exitcode << std::endl; } } return exitcode; }