Design Compiler Graphical
                            DC Ultra (TM)
                             DFTMAX (TM)
                         Power Compiler (TM)
                           DesignWare (R)
                           DC Expert (TM)
                         Design Vision (TM)
                          HDL Compiler (TM)
                         VHDL Compiler (TM)
                            DFT Compiler
                        Library Compiler (TM)
                         Design Compiler(R)

          Version J-2014.09-SP3 for RHEL64 -- Jan 19, 2015
               Copyright (c) 1988-2015 Synopsys, Inc.

This software and the associated documentation are confidential and 
proprietary to Synopsys, Inc. Your use or disclosure of this software 
is subject to the terms and conditions of a written license agreement 
between you, or your company, and Synopsys, Inc.

Initializing...
set search_path			[concat ../models/memory/cln28hpm/rf2_128x128_wm1 ../models/memory/cln28hpm/rf2_256x128_wm1 ../models/memory/cln28hpm/rf2_256_19_wm0 ../models/memory/cln28hpm/rf2_32x128_wm1  ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache]
../models/memory/cln28hpm/rf2_128x128_wm1 ../models/memory/cln28hpm/rf2_256x128_wm1 ../models/memory/cln28hpm/rf2_256_19_wm0 ../models/memory/cln28hpm/rf2_32x128_wm1 ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache
set link_library		[concat NanGate_15nm_OCL.db]
NanGate_15nm_OCL.db
set symbol_library		{}
set target_library		[concat NanGate_15nm_OCL.db]
NanGate_15nm_OCL.db
set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_bank_valid.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v rf2_128x128_wm1.v 					]
VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_bank_valid.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v rf2_128x128_wm1.v
# set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v # 					]
set top_level Vortex
Vortex
analyze -format sverilog $verilog_files
Running PRESTO HDLC
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_countones.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_countones.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_countones.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_countones.v
Searching for ../rtl/VX_countones.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_priority_encoder_w_mask.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_priority_encoder_w_mask.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_priority_encoder_w_mask.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_priority_encoder_w_mask.v
Searching for ../rtl/VX_priority_encoder_w_mask.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_dram_req_rsp_inter.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_dram_req_rsp_inter.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_dram_req_rsp_inter.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_dram_req_rsp_inter.v
Searching for ../rtl/VX_dram_req_rsp_inter.v
Searching for ../rtl/interfaces/VX_dram_req_rsp_inter.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_cache_bank_valid.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_cache_bank_valid.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_cache_bank_valid.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_cache_bank_valid.v
Searching for ../rtl/VX_cache_bank_valid.v
Searching for ../rtl/interfaces/VX_cache_bank_valid.v
Searching for ../rtl/pipe_regs/VX_cache_bank_valid.v
Searching for ../rtl/shared_memory/VX_cache_bank_valid.v
Searching for ../rtl/cache/VX_cache_bank_valid.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_cache_data_per_index.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_cache_data_per_index.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_cache_data_per_index.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_cache_data_per_index.v
Searching for ../rtl/VX_cache_data_per_index.v
Searching for ../rtl/interfaces/VX_cache_data_per_index.v
Searching for ../rtl/pipe_regs/VX_cache_data_per_index.v
Searching for ../rtl/shared_memory/VX_cache_data_per_index.v
Searching for ../rtl/cache/VX_cache_data_per_index.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_Cache_Bank.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_Cache_Bank.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_Cache_Bank.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_Cache_Bank.v
Searching for ../rtl/VX_Cache_Bank.v
Searching for ../rtl/interfaces/VX_Cache_Bank.v
Searching for ../rtl/pipe_regs/VX_Cache_Bank.v
Searching for ../rtl/shared_memory/VX_Cache_Bank.v
Searching for ../rtl/cache/VX_Cache_Bank.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_cache_data.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_cache_data.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_cache_data.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_cache_data.v
Searching for ../rtl/VX_cache_data.v
Searching for ../rtl/interfaces/VX_cache_data.v
Searching for ../rtl/pipe_regs/VX_cache_data.v
Searching for ../rtl/shared_memory/VX_cache_data.v
Searching for ../rtl/cache/VX_cache_data.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_d_cache.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_d_cache.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_d_cache.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_d_cache.v
Searching for ../rtl/VX_d_cache.v
Searching for ../rtl/interfaces/VX_d_cache.v
Searching for ../rtl/pipe_regs/VX_d_cache.v
Searching for ../rtl/shared_memory/VX_d_cache.v
Searching for ../rtl/cache/VX_d_cache.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_bank_valids.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_bank_valids.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_bank_valids.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_bank_valids.v
Searching for ../rtl/VX_bank_valids.v
Searching for ../rtl/interfaces/VX_bank_valids.v
Searching for ../rtl/pipe_regs/VX_bank_valids.v
Searching for ../rtl/shared_memory/VX_bank_valids.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_priority_encoder_sm.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_priority_encoder_sm.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_priority_encoder_sm.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_priority_encoder_sm.v
Searching for ../rtl/VX_priority_encoder_sm.v
Searching for ../rtl/interfaces/VX_priority_encoder_sm.v
Searching for ../rtl/pipe_regs/VX_priority_encoder_sm.v
Searching for ../rtl/shared_memory/VX_priority_encoder_sm.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_shared_memory.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_shared_memory.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_shared_memory.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_shared_memory.v
Searching for ../rtl/VX_shared_memory.v
Searching for ../rtl/interfaces/VX_shared_memory.v
Searching for ../rtl/pipe_regs/VX_shared_memory.v
Searching for ../rtl/shared_memory/VX_shared_memory.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_shared_memory_block.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_shared_memory_block.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_shared_memory_block.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_shared_memory_block.v
Searching for ../rtl/VX_shared_memory_block.v
Searching for ../rtl/interfaces/VX_shared_memory_block.v
Searching for ../rtl/pipe_regs/VX_shared_memory_block.v
Searching for ../rtl/shared_memory/VX_shared_memory_block.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_dmem_controller.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_dmem_controller.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_dmem_controller.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_dmem_controller.v
Searching for ../rtl/VX_dmem_controller.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_generic_priority_encoder.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_generic_priority_encoder.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_generic_priority_encoder.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_generic_priority_encoder.v
Searching for ../rtl/VX_generic_priority_encoder.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_generic_stack.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_generic_stack.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_generic_stack.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_generic_stack.v
Searching for ../rtl/VX_generic_stack.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_join_inter.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_join_inter.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_join_inter.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_join_inter.v
Searching for ../rtl/VX_join_inter.v
Searching for ../rtl/interfaces/VX_join_inter.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_csr_wrapper.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_csr_wrapper.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_csr_wrapper.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_csr_wrapper.v
Searching for ../rtl/VX_csr_wrapper.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_csr_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_csr_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_csr_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_csr_req_inter.v
Searching for ../rtl/VX_csr_req_inter.v
Searching for ../rtl/interfaces/VX_csr_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_csr_wb_inter.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_csr_wb_inter.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_csr_wb_inter.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_csr_wb_inter.v
Searching for ../rtl/VX_csr_wb_inter.v
Searching for ../rtl/interfaces/VX_csr_wb_inter.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_gpgpu_inst.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_gpgpu_inst.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_gpgpu_inst.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_gpgpu_inst.v
Searching for ../rtl/VX_gpgpu_inst.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_gpu_inst_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_gpu_inst_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_gpu_inst_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_gpu_inst_req_inter.v
Searching for ../rtl/VX_gpu_inst_req_inter.v
Searching for ../rtl/interfaces/VX_gpu_inst_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_wstall_inter.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_wstall_inter.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_wstall_inter.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_wstall_inter.v
Searching for ../rtl/VX_wstall_inter.v
Searching for ../rtl/interfaces/VX_wstall_inter.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_inst_exec_wb_inter.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_inst_exec_wb_inter.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_inst_exec_wb_inter.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_inst_exec_wb_inter.v
Searching for ../rtl/VX_inst_exec_wb_inter.v
Searching for ../rtl/interfaces/VX_inst_exec_wb_inter.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_lsu.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_lsu.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_lsu.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_lsu.v
Searching for ../rtl/VX_lsu.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_execute_unit.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_execute_unit.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_execute_unit.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_execute_unit.v
Searching for ../rtl/VX_execute_unit.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_lsu_addr_gen.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_lsu_addr_gen.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_lsu_addr_gen.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_lsu_addr_gen.v
Searching for ../rtl/VX_lsu_addr_gen.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_inst_multiplex.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_inst_multiplex.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_inst_multiplex.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_inst_multiplex.v
Searching for ../rtl/VX_inst_multiplex.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_exec_unit_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_exec_unit_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_exec_unit_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_exec_unit_req_inter.v
Searching for ../rtl/VX_exec_unit_req_inter.v
Searching for ../rtl/interfaces/VX_exec_unit_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_lsu_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_lsu_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_lsu_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_lsu_req_inter.v
Searching for ../rtl/VX_lsu_req_inter.v
Searching for ../rtl/interfaces/VX_lsu_req_inter.v
Searching for ../models/memory/cln28hpm/rf2_128x128_wm1/VX_alu.v
Searching for ../models/memory/cln28hpm/rf2_256x128_wm1/VX_alu.v
Searching for ../models/memory/cln28hpm/rf2_256_19_wm0/VX_alu.v
Searching for ../models/memory/cln28hpm/rf2_32x128_wm1/VX_alu.v
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Compiling source file ../rtl/VX_countones.v
Compiling source file ../rtl/VX_priority_encoder_w_mask.v
Opening include file ../rtl/interfaces/../VX_define.v
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Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_dram_req_rsp_inter.v:10: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/cache/VX_cache_bank_valid.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Opening include file ../rtl/interfaces/../VX_define.v
Compiling source file ../rtl/shared_memory/VX_bank_valids.v
Opening include file ../rtl/interfaces/../VX_define.v
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Opening include file ../rtl/interfaces/../VX_define.v
Compiling source file ../rtl/shared_memory/VX_shared_memory.v
Opening include file ../rtl/interfaces/../VX_define.v
Compiling source file ../rtl/shared_memory/VX_shared_memory_block.v
Compiling source file ../rtl/VX_dmem_controller.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_generic_priority_encoder.v
Opening include file ../rtl/interfaces/../VX_define.v
Compiling source file ../rtl/VX_generic_stack.v
Compiling source file ../rtl/interfaces/VX_join_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_join_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/VX_csr_wrapper.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/interfaces/VX_csr_req_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_csr_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_csr_wb_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_csr_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/VX_gpgpu_inst.v
Opening include file ../rtl//VX_define.v
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Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_gpu_inst_req_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_wstall_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_wstall_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_inst_exec_wb_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_inst_exec_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/VX_lsu.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_execute_unit.v
Opening include file ../rtl//VX_define.v
Warning:  ../rtl/VX_lsu.v:59: Invalid escape sequence '\x' in call to '$display'. (VER-941)
Warning:  ../rtl/VX_lsu.v:59: Invalid escape sequence '\x' in call to '$display'. (VER-941)
Warning:  ../rtl/VX_lsu.v:63: Invalid escape sequence '\x' in call to '$display'. (VER-941)
Warning:  ../rtl/VX_lsu.v:63: Invalid escape sequence '\x' in call to '$display'. (VER-941)
Compiling source file ../rtl/VX_lsu_addr_gen.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_inst_multiplex.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/interfaces/VX_exec_unit_req_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_exec_unit_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_lsu_req_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_lsu_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/VX_alu.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_back_end.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_gpr_stage.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/interfaces/VX_gpr_data_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_gpr_data_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/VX_csr_handler.v
Compiling source file ../rtl/VX_decode.v
Opening include file ../rtl//VX_define.v
Warning:  ../rtl/VX_csr_handler.v:41: The statements in initial blocks are ignored. (VER-281)
Compiling source file ../rtl/VX_define.v
Compiling source file ../rtl/VX_scheduler.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_fetch.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_front_end.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_generic_register.v
Compiling source file ../rtl/VX_gpr.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_gpr_wrapper.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_priority_encoder.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_warp_scheduler.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/VX_writeback.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/byte_enabled_simple_dual_port_ram.v
Opening include file ../rtl//VX_define.v
Compiling source file ../rtl/interfaces/VX_branch_response_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_branch_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_dcache_request_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_dcache_request_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_dcache_response_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_dcache_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_frE_to_bckE_req_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_frE_to_bckE_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_gpr_clone_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_gpr_clone_inter.v:9: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_gpr_jal_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_gpr_jal_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_gpr_read_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_gpr_read_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_gpr_wspawn_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_gpr_wspawn_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_icache_request_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_icache_request_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_icache_response_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_icache_response_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_inst_mem_wb_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_inst_mem_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_inst_meta_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_inst_meta_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_jal_response_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_jal_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_mem_req_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_mem_req_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_mw_wb_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_mw_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_warp_ctl_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_warp_ctl_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/interfaces/VX_wb_inter.v
Opening include file ../rtl/interfaces/../VX_define.v
Information:  ../rtl/interfaces/VX_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
Compiling source file ../rtl/pipe_regs/VX_d_e_reg.v
Opening include file ../rtl/interfaces/../VX_define.v
Compiling source file ../rtl/pipe_regs/VX_f_d_reg.v
Opening include file ../rtl/interfaces/../VX_define.v
Compiling source file ../rtl/Vortex.v
Opening include file ../rtl/interfaces/../VX_define.v
Compiling source file ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:15443: real declarations are not supported by synthesis. (VER-177)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:15444: real declarations are not supported by synthesis. (VER-177)
Warning:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16365: delays for continuous assignment are ignored. (VER-173)
Warning:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16366: delays for continuous assignment are ignored. (VER-173)
Warning:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16367: delays for continuous assignment are ignored. (VER-173)
Warning:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16368: delays for continuous assignment are ignored. (VER-173)
Warning:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16369: delays for continuous assignment are ignored. (VER-173)
Warning:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16370: delays for continuous assignment are ignored. (VER-173)
Warning:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16371: delays for continuous assignment are ignored. (VER-173)
Warning:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16372: delays for continuous assignment are ignored. (VER-173)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16408: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16408: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16415: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16428: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16428: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16516: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16516: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16561: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16561: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16646: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16646: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16685: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16685: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16687: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16687: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16689: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16689: case equality (===) is not supported by synthesis. (VER-189)
Error:  ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v:16692: case equality (===) is not supported by synthesis. (VER-189)
Error:  Too many errors; can't continue. (VER-40)
*** Presto compilation terminated with 21 errors. ***
Warning: Can't read link_library file 'NanGate_15nm_OCL.db'. (UID-3)
0
elaborate Vortex
Loading db file '/tools/synopsys/synthesis/j201409sp3/libraries/syn/gtech.db'
Loading db file '/tools/synopsys/synthesis/j201409sp3/libraries/syn/standard.sldb'
  Loading link library 'gtech'
Warning: Can't read link_library file 'NanGate_15nm_OCL.db'. (UID-3)
Running PRESTO HDLC
Presto compilation completed successfully.
Elaborated 1 design.
Current design is now 'Vortex'.
Warning: Can't read link_library file 'NanGate_15nm_OCL.db'. (UID-3)
Information: Building the design 'VX_front_end' instantiated from design 'Vortex' with
	the parameters "|((N%clk%)(N%reset%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%schedule_delay%)(N%icache_response_fe%I%WORK/VX_icache_response_inter%%)(N%icache_request_fe%I%WORK/VX_icache_request_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%fetch_ebreak%))". (HDL-193)
Presto compilation completed successfully.
Warning: Filename too long >255 chars. Renaming file:
'/nethome/felsabbagh3/research/UseVortex/syn/VX_FRONT_END_I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_ICACHE_RESPONSE_FE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_FE_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__.mr'
to
'/nethome/felsabbagh3/research/UseVortex/syn/VX_FRONT_END_I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_ICACHE_RESPONSE_FE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_FE_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_35FE527370C98E3C09E2E6E2555D7EE6F02ECB4FA9775364_000.mr'
Information: Building the design 'VX_scheduler' instantiated from design 'Vortex' with
	the parameters "|((N%clk%)(N%reset%)(N%memory_delay%)(N%gpr_stage_delay%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%schedule_delay%))". (HDL-193)

Inferred memory devices in process
	in routine VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__ line 52 in file
		'../rtl/VX_scheduler.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  rename_table_reg   | Flip-flop |  256  |  N  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
=====================================================================================================================================
|                                      block name/line                                       | Inputs | Outputs | # sel inputs | MB |
=====================================================================================================================================
| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/24 |   8    |   32    |      3       | N  |
| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/24 |   32   |    1    |      5       | N  |
| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/25 |   32   |    1    |      5       | N  |
=====================================================================================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_back_end' instantiated from design 'Vortex' with
	the parameters "|((N%clk%)(N%reset%)(N%schedule_delay%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%out_mem_delay%)(N%gpr_stage_delay%))". (HDL-193)
Presto compilation completed successfully.
Warning: Filename too long >255 chars. Renaming file:
'/nethome/felsabbagh3/research/UseVortex/syn/VX_BACK_END_I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__I_VX_WRITEBACK_INTER_VX_WB_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_VX_DCACHE_RSP_VX_DCACHE_RESPONSE_INTER__I_VX_DCACHE_REQ_VX_DCACHE_REQUEST_INTER__.mr'
to
'/nethome/felsabbagh3/research/UseVortex/syn/VX_BACK_END_I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__I_VX_WRITEBACK_INTER_VX_WB_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__I__B458045CB598257C352A6473E41AFB0017DAE536C3121AF6_000.mr'
Information: Building the design 'VX_dmem_controller' instantiated from design 'Vortex' with
	the parameters "|((N%clk%)(N%reset%)(N%VX_dram_req_rsp%I%WORK/VX_dram_req_rsp_inter%%NUMBER_BANKS=4,NUM_WORDS_PER_BLOCK=4)(N%VX_dram_req_rsp_icache%I%WORK/VX_dram_req_rsp_inter%%NUMBER_BANKS=1,NUM_WORDS_PER_BLOCK=4)(N%VX_icache_req%I%WORK/VX_icache_request_inter%%)(N%VX_icache_rsp%I%WORK/VX_icache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%))". (HDL-193)
Warning:  ../rtl/VX_dmem_controller.v:94: signed to unsigned conversion occurs. (VER-318)
Warning:  ../rtl/VX_dmem_controller.v:140: signed to unsigned conversion occurs. (VER-318)
Presto compilation completed successfully.
Warning: Filename too long >255 chars. Renaming file:
'/nethome/felsabbagh3/research/UseVortex/syn/VX_DMEM_CONTROLLER_I_VX_DRAM_REQ_RSP_VX_DRAM_REQ_RSP_INTER__NUMBER_BANKS_4_NUM_WORDS_PER_BLOCK_4I_VX_DRAM_REQ_RSP_ICACHE_VX_DRAM_REQ_RSP_INTER__NUMBER_BANKS_1_NUM_WORDS_PER_BLOCK_4I_VX_ICACHE_REQ_VX_ICACHE_REQUEST_INTER__I_VX_ICACHE_RSP_VX_ICACHE_RESPONSE_INTER__I_VX_DCACHE_REQ_VX_DCACHE_REQUEST_INTER__I_VX_DCACHE_RSP_VX_DCACHE_RESPONSE_INTER__.mr'
to
'/nethome/felsabbagh3/research/UseVortex/syn/VX_DMEM_CONTROLLER_I_VX_DRAM_REQ_RSP_VX_DRAM_REQ_RSP_INTER__NUMBER_BANKS_4_NUM_WORDS_PER_BLOCK_4I_VX_DRAM_REQ_RSP_ICACHE_VX_DRAM_REQ_RSP_INTER__NUMBER_BANKS_1_NUM_WORDS_PER_BLOCK_4I_VX_ICACHE_REQ_VX__40031EEB97323B6857B566A3D5CC469DED662C572979AF0C_000.mr'
Information: Building the design 'VX_fetch' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
	the parameters "|((N%clk%)(N%reset%)(N%VX_wstall%I%WORK/VX_wstall_inter%%)(N%VX_join%I%WORK/VX_join_inter%%)(N%schedule_delay%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%icache_response%I%WORK/VX_icache_response_inter%%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%icache_request%I%WORK/VX_icache_request_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%out_ebreak%)(N%fe_inst_meta_fd%I%WORK/VX_inst_meta_inter%%))". (HDL-193)
Presto compilation completed successfully.
Warning: Filename too long >255 chars. Renaming file:
'/nethome/felsabbagh3/research/UseVortex/syn/VX_FETCH_I_VX_WSTALL_VX_WSTALL_INTER__I_VX_JOIN_VX_JOIN_INTER__I_ICACHE_RESPONSE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_FE_INST_META_FD_VX_INST_META_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__.mr'
to
'/nethome/felsabbagh3/research/UseVortex/syn/VX_FETCH_I_VX_WSTALL_VX_WSTALL_INTER__I_VX_JOIN_VX_JOIN_INTER__I_ICACHE_RESPONSE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RS_86A42238AAF2AFE24C53E826055B694A355B7E541802DCF6_000.mr'
Information: Building the design 'VX_f_d_reg' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
	the parameters "|((N%clk%)(N%reset%)(N%in_freeze%)(N%fe_inst_meta_fd%I%WORK/VX_inst_meta_inter%%)(N%fd_inst_meta_de%I%WORK/VX_inst_meta_inter%%))". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_decode' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
	the parameters "|((N%fd_inst_meta_de%I%WORK/VX_inst_meta_inter%%)(N%VX_frE_to_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_wstall%I%WORK/VX_wstall_inter%%)(N%VX_join%I%WORK/VX_join_inter%%))". (HDL-193)
Warning:  ../rtl/VX_decode.v:152: signed to unsigned assignment occurs. (VER-318)
Warning:  ../rtl/VX_decode.v:300: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
Warning:  ../rtl/VX_decode.v:315: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)

Statistics for case statements in always block at line 159 in file
	'../rtl/VX_decode.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           160            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 190 in file
	'../rtl/VX_decode.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           191            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 244 in file
	'../rtl/VX_decode.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           245            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 258 in file
	'../rtl/VX_decode.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           259            |    auto/auto     |
|           264            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 298 in file
	'../rtl/VX_decode.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           300            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 313 in file
	'../rtl/VX_decode.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           315            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 330 in file
	'../rtl/VX_decode.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           331            |    auto/auto     |
===============================================
Presto compilation completed successfully.
Information: Building the design 'VX_d_e_reg' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
	the parameters "|((N%clk%)(N%reset%)(N%in_branch_stall%)(N%in_freeze%)(N%VX_frE_to_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%))". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_mw_wb_inter'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_mem_req_inter'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_gpr_stage' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
	the parameters "|((N%clk%)(N%reset%)(N%schedule_delay%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_csr_req%I%WORK/VX_csr_req_inter%%)(N%memory_delay%)(N%gpr_stage_delay%))". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_lsu' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
	the parameters "|((N%clk%)(N%reset%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_mem_wb%I%WORK/VX_inst_mem_wb_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%out_delay%)(N%no_slot_mem%))". (HDL-193)
Warning:  ../rtl/VX_lsu.v:59: Invalid escape sequence '\x' in call to '$display'. (VER-941)
Warning:  ../rtl/VX_lsu.v:59: Invalid escape sequence '\x' in call to '$display'. (VER-941)
Warning:  ../rtl/VX_lsu.v:63: Invalid escape sequence '\x' in call to '$display'. (VER-941)
Warning:  ../rtl/VX_lsu.v:63: Invalid escape sequence '\x' in call to '$display'. (VER-941)
$display output: Reading addr:  val: ??
$display output: Writing addr:  val: ??
$display output: Reading addr:  val: ??
$display output: Writing addr:  val: ??
$display output: Reading addr:  val: ??
$display output: Writing addr:  val: ??
$display output: Reading addr:  val: ??
$display output: Writing addr:  val: ??
Warning:  ../rtl/VX_lsu.v:55: Netlist for always block is empty. (ELAB-985)
Presto compilation completed successfully.
Information: Building the design 'VX_execute_unit' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
	the parameters "|((N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_inst_exec_wb%I%WORK/VX_inst_exec_wb_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%))". (HDL-193)
Warning:  ../rtl/VX_execute_unit.v:108: signed to unsigned assignment occurs. (VER-318)
Warning:  ../rtl/VX_execute_unit.v:115: signed to unsigned assignment occurs. (VER-318)

Statistics for case statements in always block at line 74 in file
	'../rtl/VX_execute_unit.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            76            |    auto/auto     |
===============================================
Statistics for MUX_OPs
================================================================================================================================================================================================================================
|                                                                                   block name/line                                                                                     | Inputs | Outputs | # sel inputs | MB |
================================================================================================================================================================================================================================
| VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__/71 |   4    |   64    |      2       | N  |
================================================================================================================================================================================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_gpgpu_inst' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
	the parameters "|((N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%))". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_csr_wrapper' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
	the parameters "|((N%VX_csr_req%I%WORK/VX_csr_req_inter%%)(N%VX_csr_wb%I%WORK/VX_csr_wb_inter%%))". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_writeback' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
	the parameters "|((N%VX_mem_wb%I%WORK/VX_inst_mem_wb_inter%%)(N%VX_inst_exec_wb%I%WORK/VX_inst_exec_wb_inter%%)(N%VX_csr_wb%I%WORK/VX_csr_wb_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%no_slot_mem%))". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_shared_memory' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__NUMBER_BANKS_4_NUM_WORDS_PER_BLOCK_4I_VX_dram_req_rsp_icache_VX_dram_req_rsp_inter__NUMBER_BANKS_1_NUM_WORDS_PER_BLOCK_4I_VX_icache_req_VX_icache_request_inter__I_VX_icache_rsp_VX_icache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with
	the parameters "NB=7,BITS_PER_BANK=3". (HDL-193)

Inferred memory devices in process
	in routine VX_shared_memory_NB7_BITS_PER_BANK3 line 86 in file
		'../rtl/shared_memory/VX_shared_memory.v'.
===========================================================================
|    Register Name    | Type  | Width | Bus | MB | AR | AS | SR | SS | ST |
===========================================================================
|  temp_out_data_reg  | Latch |   5   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   5   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   5   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   5   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|  temp_out_data_reg  | Latch |   9   |  Y  | N  | N  | N  | -  | -  | -  |
|    shm_write_reg    | Latch |   1   |  N  | N  | N  | N  | -  | -  | -  |
| temp_out_valid_reg  | Latch |   4   |  N  | N  | N  | N  | -  | -  | -  |
===========================================================================
Statistics for MUX_OPs
==================================================================================
|            block name/line              | Inputs | Outputs | # sel inputs | MB |
==================================================================================
| VX_shared_memory_NB7_BITS_PER_BANK3/122 |   4    |   32    |      2       | N  |
| VX_shared_memory_NB7_BITS_PER_BANK3/122 |   4    |   32    |      2       | N  |
| VX_shared_memory_NB7_BITS_PER_BANK3/122 |   4    |   32    |      2       | N  |
| VX_shared_memory_NB7_BITS_PER_BANK3/122 |   4    |   32    |      2       | N  |
| VX_shared_memory_NB7_BITS_PER_BANK3/122 |   4    |   32    |      2       | N  |
| VX_shared_memory_NB7_BITS_PER_BANK3/122 |   4    |   32    |      2       | N  |
| VX_shared_memory_NB7_BITS_PER_BANK3/122 |   4    |   32    |      2       | N  |
| VX_shared_memory_NB7_BITS_PER_BANK3/122 |   4    |   32    |      2       | N  |
==================================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_d_cache' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__NUMBER_BANKS_4_NUM_WORDS_PER_BLOCK_4I_VX_dram_req_rsp_icache_VX_dram_req_rsp_inter__NUMBER_BANKS_1_NUM_WORDS_PER_BLOCK_4I_VX_icache_req_VX_icache_request_inter__I_VX_icache_rsp_VX_icache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with
	the parameters "CACHE_SIZE=4096,CACHE_WAYS=2,CACHE_BLOCK=64,CACHE_BANKS=4,LOG_NUM_BANKS=2,NUM_REQ=4,LOG_NUM_REQ=2,NUM_IND=32,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,OFFSET_SIZE_START=0,OFFSET_SIZE_END=1,TAG_SIZE_START=0,TAG_SIZE_END=20,IND_SIZE_START=0,IND_SIZE_END=4,ADDR_TAG_START=11,ADDR_TAG_END=31,ADDR_OFFSET_START=4,ADDR_OFFSET_END=5,ADDR_IND_START=6,ADDR_IND_END=10,MEM_ADDR_REQ_MASK=32'hffffffc0". (HDL-193)
Warning:  ../rtl/cache/VX_d_cache.v:237: signed to unsigned assignment occurs. (VER-318)

Inferred memory devices in process
	in routine VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0 line 251 in file
		'../rtl/cache/VX_d_cache.v'.
===================================================================================
|      Register Name      |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===================================================================================
| global_way_to_evict_reg | Flip-flop |   1   |  N  | N  | Y  | N  | N  | N  | N  |
|   final_data_read_reg   | Flip-flop |  128  |  Y  | N  | Y  | N  | N  | N  | N  |
|        state_reg        | Flip-flop |   4   |  Y  | N  | Y  | N  | N  | N  | N  |
|    stored_valid_reg     | Flip-flop |   4   |  Y  | N  | Y  | N  | N  | N  | N  |
|      miss_addr_reg      | Flip-flop |  30   |  Y  | N  | Y  | N  | N  | N  | N  |
===================================================================================
Statistics for MUX_OPs
=======================================================================================================================
|                               block name/line                                | Inputs | Outputs | # sel inputs | MB |
=======================================================================================================================
| VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0/279 |   4    |    2    |      2       | N  |
| VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0/279 |   4    |   30    |      2       | N  |
| VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0/298 |   4    |   30    |      2       | N  |
| VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0/342 |   4    |   32    |      2       | N  |
| VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0/298 |   4    |   30    |      2       | N  |
| VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0/342 |   4    |   32    |      2       | N  |
| VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0/298 |   4    |   30    |      2       | N  |
| VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0/342 |   4    |   32    |      2       | N  |
| VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0/298 |   4    |   30    |      2       | N  |
| VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0/342 |   4    |   32    |      2       | N  |
=======================================================================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_d_cache' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__NUMBER_BANKS_4_NUM_WORDS_PER_BLOCK_4I_VX_dram_req_rsp_icache_VX_dram_req_rsp_inter__NUMBER_BANKS_1_NUM_WORDS_PER_BLOCK_4I_VX_icache_req_VX_icache_request_inter__I_VX_icache_rsp_VX_icache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with
	the parameters "CACHE_SIZE=1024,CACHE_WAYS=2,CACHE_BLOCK=16,CACHE_BANKS=1,LOG_NUM_BANKS=1,NUM_REQ=1,LOG_NUM_REQ=1,NUM_IND=32,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,OFFSET_SIZE_START=0,OFFSET_SIZE_END=1,TAG_SIZE_START=0,TAG_SIZE_END=22,IND_SIZE_START=0,IND_SIZE_END=4,ADDR_TAG_START=9,ADDR_TAG_END=31,ADDR_OFFSET_START=2,ADDR_OFFSET_END=3,ADDR_IND_START=4,ADDR_IND_END=8,MEM_ADDR_REQ_MASK=32'hfffffff0". (HDL-193)
Warning:  ../rtl/cache/VX_d_cache.v:237: signed to unsigned assignment occurs. (VER-318)

Inferred memory devices in process
	in routine VX_d_cache_1024_2_16_1_1_1_1_32_1_4_0_1_0_22_0_4_9_31_2_3_4_8_fffffff0 line 251 in file
		'../rtl/cache/VX_d_cache.v'.
===================================================================================
|      Register Name      |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===================================================================================
| global_way_to_evict_reg | Flip-flop |   1   |  N  | N  | Y  | N  | N  | N  | N  |
|   final_data_read_reg   | Flip-flop |  32   |  Y  | N  | Y  | N  | N  | N  | N  |
|        state_reg        | Flip-flop |   4   |  Y  | N  | Y  | N  | N  | N  | N  |
|    stored_valid_reg     | Flip-flop |   1   |  N  | N  | Y  | N  | N  | N  | N  |
|      miss_addr_reg      | Flip-flop |  32   |  Y  | N  | Y  | N  | N  | N  | N  |
===================================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_warp_scheduler'. (HDL-193)

Inferred memory devices in process
	in routine VX_warp_scheduler line 117 in file
		'../rtl/VX_warp_scheduler.v'.
==================================================================================
|     Register Name      |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
==================================================================================
|    warp_stalled_reg    | Flip-flop |   8   |  N  | N  | Y  | N  | N  | N  | N  |
|    didnt_split_reg     | Flip-flop |   1   |  N  | N  | Y  | N  | N  | N  | N  |
| barrier_stall_mask_reg | Flip-flop |  32   |  N  | N  | Y  | N  | N  | N  | N  |
|   use_wsapwn_pc_reg    | Flip-flop |  32   |  Y  | N  | Y  | N  | N  | N  | N  |
|     use_wsapwn_reg     | Flip-flop |   8   |  N  | N  | Y  | N  | N  | N  | N  |
|      warp_pcs_reg      | Flip-flop |  32   |  Y  | N  | Y  | N  | N  | N  | N  |
|      warp_pcs_reg      | Flip-flop |  32   |  Y  | N  | Y  | N  | N  | N  | N  |
|      warp_pcs_reg      | Flip-flop |  32   |  Y  | N  | Y  | N  | N  | N  | N  |
|      warp_pcs_reg      | Flip-flop |  32   |  Y  | N  | Y  | N  | N  | N  | N  |
|      warp_pcs_reg      | Flip-flop |  32   |  Y  | N  | Y  | N  | N  | N  | N  |
|      warp_pcs_reg      | Flip-flop |  32   |  Y  | N  | Y  | N  | N  | N  | N  |
|      warp_pcs_reg      | Flip-flop |  32   |  Y  | N  | Y  | N  | N  | N  | N  |
|      warp_pcs_reg      | Flip-flop |   3   |  Y  | N  | Y  | N  | N  | N  | N  |
|      warp_pcs_reg      | Flip-flop |  29   |  Y  | N  | N  | Y  | N  | N  | N  |
|    warp_active_reg     | Flip-flop |   7   |  N  | N  | Y  | N  | N  | N  | N  |
|    warp_active_reg     | Flip-flop |   1   |  N  | N  | N  | Y  | N  | N  | N  |
|   visible_active_reg   | Flip-flop |   7   |  N  | N  | Y  | N  | N  | N  | N  |
|   visible_active_reg   | Flip-flop |   1   |  N  | N  | N  | Y  | N  | N  | N  |
|    thread_masks_reg    | Flip-flop |   3   |  Y  | N  | Y  | N  | N  | N  | N  |
|    thread_masks_reg    | Flip-flop |   3   |  Y  | N  | Y  | N  | N  | N  | N  |
|    thread_masks_reg    | Flip-flop |   3   |  Y  | N  | Y  | N  | N  | N  | N  |
|    thread_masks_reg    | Flip-flop |   3   |  Y  | N  | Y  | N  | N  | N  | N  |
|    thread_masks_reg    | Flip-flop |   3   |  Y  | N  | Y  | N  | N  | N  | N  |
|    thread_masks_reg    | Flip-flop |   3   |  Y  | N  | Y  | N  | N  | N  | N  |
|    thread_masks_reg    | Flip-flop |   3   |  Y  | N  | Y  | N  | N  | N  | N  |
|    thread_masks_reg    | Flip-flop |   3   |  Y  | N  | Y  | N  | N  | N  | N  |
|    thread_masks_reg    | Flip-flop |   8   |  N  | N  | N  | Y  | N  | N  | N  |
==================================================================================
Statistics for MUX_OPs
================================================================
|   block name/line     | Inputs | Outputs | # sel inputs | MB |
================================================================
| VX_warp_scheduler/227 |   4    |    8    |      2       | N  |
| VX_warp_scheduler/245 |   8    |    4    |      3       | N  |
| VX_warp_scheduler/249 |   8    |   37    |      3       | N  |
| VX_warp_scheduler/278 |   8    |    3    |      3       | N  |
| VX_warp_scheduler/286 |   8    |   32    |      3       | N  |
| VX_warp_scheduler/287 |   8    |    4    |      3       | N  |
================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_generic_register' instantiated from design 'VX_f_d_reg_I_fe_inst_meta_fd_VX_inst_meta_inter__I_fd_inst_meta_de_VX_inst_meta_inter__' with
	the parameters "N=71". (HDL-193)

Inferred memory devices in process
	in routine VX_generic_register_N71 line 21 in file
		'../rtl/VX_generic_register.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      value_reg      | Flip-flop |  71   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_generic_register' instantiated from design 'VX_d_e_reg_I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
	the parameters "N=240". (HDL-193)

Inferred memory devices in process
	in routine VX_generic_register_N240 line 21 in file
		'../rtl/VX_generic_register.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      value_reg      | Flip-flop |  240  |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_gpr_wrapper' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
	the parameters "|((N%clk%)(N%reset%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%VX_gpr_read%I%WORK/VX_gpr_read_inter%%)(N%VX_gpr_jal%I%WORK/VX_gpr_jal_inter%%)(N%out_a_reg_data%)(N%out_b_reg_data%))". (HDL-193)
Statistics for MUX_OPs
===============================================================================================================================================================
|                                                   block name/line                                                    | Inputs | Outputs | # sel inputs | MB |
===============================================================================================================================================================
| VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__/42 |   8    |   256   |      3       | N  |
===============================================================================================================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_inst_multiplex' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
	the parameters "|((N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_gpr_data%I%WORK/VX_gpr_data_inter%%)(N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_csr_req%I%WORK/VX_csr_req_inter%%))". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
	the parameters "N=1". (HDL-193)

Inferred memory devices in process
	in routine VX_generic_register_N1 line 21 in file
		'../rtl/VX_generic_register.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      value_reg      | Flip-flop |   1   |  N  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
	the parameters "N=256". (HDL-193)

Inferred memory devices in process
	in routine VX_generic_register_N256 line 21 in file
		'../rtl/VX_generic_register.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      value_reg      | Flip-flop |  256  |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
	the parameters "N=84". (HDL-193)

Inferred memory devices in process
	in routine VX_generic_register_N84 line 21 in file
		'../rtl/VX_generic_register.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      value_reg      | Flip-flop |  84   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
	the parameters "N=231". (HDL-193)

Inferred memory devices in process
	in routine VX_generic_register_N231 line 21 in file
		'../rtl/VX_generic_register.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      value_reg      | Flip-flop |  231  |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
	the parameters "N=43". (HDL-193)

Inferred memory devices in process
	in routine VX_generic_register_N43 line 21 in file
		'../rtl/VX_generic_register.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      value_reg      | Flip-flop |  43   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
	the parameters "N=60". (HDL-193)

Inferred memory devices in process
	in routine VX_generic_register_N60 line 21 in file
		'../rtl/VX_generic_register.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      value_reg      | Flip-flop |  60   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_lsu_addr_gen'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_alu'. (HDL-193)
Warning:  ../rtl/VX_alu.v:40: signed to unsigned assignment occurs. (VER-318)
Warning:  ../rtl/VX_alu.v:49: signed to unsigned assignment occurs. (VER-318)
Warning:  ../rtl/VX_alu.v:50: signed to unsigned assignment occurs. (VER-318)
Warning:  ../rtl/VX_alu.v:56: signed to unsigned assignment occurs. (VER-318)
Warning:  ../rtl/VX_alu.v:61: signed to unsigned assignment occurs. (VER-318)
Warning:  ../rtl/VX_alu.v:66: signed to unsigned conversion occurs. (VER-318)
Warning:  ../rtl/VX_alu.v:68: signed to unsigned conversion occurs. (VER-318)

Statistics for case statements in always block at line 47 in file
	'../rtl/VX_alu.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            48            |    auto/auto     |
===============================================
Presto compilation completed successfully.
Information: Building the design 'VX_generic_priority_encoder' instantiated from design 'VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__' with
	the parameters "N=4". (HDL-193)
Warning:  ../rtl/VX_generic_priority_encoder.v:22: signed to unsigned part selection occurs. (VER-318)
Presto compilation completed successfully.
Information: Building the design 'VX_countones' instantiated from design 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__' with
	the parameters "N=4". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_priority_encoder_sm' instantiated from design 'VX_shared_memory_NB7_BITS_PER_BANK3' with
	the parameters "NB=7,BITS_PER_BANK=3". (HDL-193)

Inferred memory devices in process
	in routine VX_priority_encoder_sm_NB7_BITS_PER_BANK3 line 104 in file
		'../rtl/shared_memory/VX_priority_encoder_sm.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  left_requests_reg  | Flip-flop |   4   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
=======================================================================================
|               block name/line                | Inputs | Outputs | # sel inputs | MB |
=======================================================================================
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 |   4    |   64    |      2       | N  |
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 |   4    |   64    |      2       | N  |
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 |   4    |   64    |      2       | N  |
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 |   4    |   64    |      2       | N  |
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 |   4    |   64    |      2       | N  |
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 |   4    |   64    |      2       | N  |
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 |   4    |   64    |      2       | N  |
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 |   4    |   64    |      2       | N  |
=======================================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_shared_memory_block'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_cache_bank_valid' instantiated from design 'VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0' with
	the parameters "NUMBER_BANKS=4,LOG_NUM_BANKS=2,NUM_REQ=4". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_priority_encoder_w_mask' instantiated from design 'VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0' with
	the parameters "N=4". (HDL-193)
Warning:  ../rtl/VX_priority_encoder_w_mask.v:23: signed to unsigned part selection occurs. (VER-318)
Warning:  ../rtl/VX_priority_encoder_w_mask.v:31: signed to unsigned assignment occurs. (VER-318)
Presto compilation completed successfully.
Information: Building the design 'VX_Cache_Bank' instantiated from design 'VX_d_cache_4096_2_64_4_2_4_2_32_1_4_0_1_0_20_0_4_11_31_4_5_6_10_ffffffc0' with
	the parameters "CACHE_SIZE=4096,CACHE_WAYS=2,CACHE_BLOCK=64,CACHE_BANKS=4,LOG_NUM_BANKS=2,NUM_REQ=4,LOG_NUM_REQ=2,NUM_IND=32,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,OFFSET_SIZE_START=0,OFFSET_SIZE_END=1,TAG_SIZE_START=0,TAG_SIZE_END=20,IND_SIZE_START=0,IND_SIZE_END=4,ADDR_TAG_START=11,ADDR_TAG_END=31,ADDR_OFFSET_START=4,ADDR_OFFSET_END=5,ADDR_IND_START=6,ADDR_IND_END=10". (HDL-193)
Warning:  ../rtl/cache/VX_Cache_Bank.v:216: Net way_to_update[0] or a directly connected net may be driven by more than one process or block. (ELAB-405)
Statistics for MUX_OPs
===========================================================================================================================================================================================================================================================================================================================================================================================================
|                                                                                                                                                                         block name/line                                                                                                                                                                          | Inputs | Outputs | # sel inputs | MB |
===========================================================================================================================================================================================================================================================================================================================================================================================================
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START11_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END10/158 |   4    |   32    |      2       | N  |
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START11_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END10/158 |   4    |   24    |      2       | N  |
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START11_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END10/158 |   4    |   16    |      2       | N  |
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START11_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END10/158 |   4    |    8    |      2       | N  |
===========================================================================================================================================================================================================================================================================================================================================================================================================
Presto compilation completed successfully.
Warning: Filename too long >255 chars. Renaming file:
'/nethome/felsabbagh3/research/UseVortex/syn/VX_CACHE_BANK_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START11_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END10.mr'
to
'/nethome/felsabbagh3/research/UseVortex/syn/VX_CACHE_BANK_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_S_537630905D4739C0E486C3ED611033A5BC0FF1DECD31D8DB_000.mr'
Information: Building the design 'VX_cache_bank_valid' instantiated from design 'VX_d_cache_1024_2_16_1_1_1_1_32_1_4_0_1_0_22_0_4_9_31_2_3_4_8_fffffff0' with
	the parameters "NUMBER_BANKS=1,LOG_NUM_BANKS=1,NUM_REQ=1". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_priority_encoder_w_mask' instantiated from design 'VX_d_cache_1024_2_16_1_1_1_1_32_1_4_0_1_0_22_0_4_9_31_2_3_4_8_fffffff0' with
	the parameters "N=1". (HDL-193)
Warning:  ../rtl/VX_priority_encoder_w_mask.v:23: signed to unsigned part selection occurs. (VER-318)
Warning:  ../rtl/VX_priority_encoder_w_mask.v:31: signed to unsigned assignment occurs. (VER-318)
Presto compilation completed successfully.
Information: Building the design 'VX_generic_priority_encoder' instantiated from design 'VX_d_cache_1024_2_16_1_1_1_1_32_1_4_0_1_0_22_0_4_9_31_2_3_4_8_fffffff0' with
	the parameters "N=1". (HDL-193)
Warning:  ../rtl/VX_generic_priority_encoder.v:22: signed to unsigned part selection occurs. (VER-318)
Presto compilation completed successfully.
Information: Building the design 'VX_Cache_Bank' instantiated from design 'VX_d_cache_1024_2_16_1_1_1_1_32_1_4_0_1_0_22_0_4_9_31_2_3_4_8_fffffff0' with
	the parameters "CACHE_SIZE=1024,CACHE_WAYS=2,CACHE_BLOCK=16,CACHE_BANKS=1,LOG_NUM_BANKS=1,NUM_REQ=1,LOG_NUM_REQ=1,NUM_IND=32,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,OFFSET_SIZE_START=0,OFFSET_SIZE_END=1,TAG_SIZE_START=0,TAG_SIZE_END=22,IND_SIZE_START=0,IND_SIZE_END=4,ADDR_TAG_START=9,ADDR_TAG_END=31,ADDR_OFFSET_START=2,ADDR_OFFSET_END=3,ADDR_IND_START=4,ADDR_IND_END=8". (HDL-193)
Warning:  ../rtl/cache/VX_Cache_Bank.v:216: Net way_to_update[0] or a directly connected net may be driven by more than one process or block. (ELAB-405)
Statistics for MUX_OPs
=========================================================================================================================================================================================================================================================================================================================================================================================================
|                                                                                                                                                                        block name/line                                                                                                                                                                         | Inputs | Outputs | # sel inputs | MB |
=========================================================================================================================================================================================================================================================================================================================================================================================================
| VX_Cache_Bank_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8/158 |   4    |   32    |      2       | N  |
| VX_Cache_Bank_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8/158 |   4    |   24    |      2       | N  |
| VX_Cache_Bank_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8/158 |   4    |   16    |      2       | N  |
| VX_Cache_Bank_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8/158 |   4    |    8    |      2       | N  |
=========================================================================================================================================================================================================================================================================================================================================================================================================
Presto compilation completed successfully.
Warning: Filename too long >255 chars. Renaming file:
'/nethome/felsabbagh3/research/UseVortex/syn/VX_CACHE_BANK_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8.mr'
to
'/nethome/felsabbagh3/research/UseVortex/syn/VX_CACHE_BANK_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_S_EDF18E249C9AFC7FAE86B4E8AC90C60B5789F786DECF7FD1_000.mr'
Information: Building the design 'VX_countones' instantiated from design 'VX_warp_scheduler' with
	the parameters "N=8". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_generic_stack' instantiated from design 'VX_warp_scheduler' with
	the parameters "WIDTH=37,DEPTH=3". (HDL-193)

Inferred memory devices in process
	in routine VX_generic_stack_WIDTH37_DEPTH3 line 21 in file
		'../rtl/VX_generic_stack.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      stack_reg      | Flip-flop |  37   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  37   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  37   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  37   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  37   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  37   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  37   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  37   |  Y  | N  | N  | N  | N  | N  | N  |
|       ptr_reg       | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
=============================================================================
|          block name/line           | Inputs | Outputs | # sel inputs | MB |
=============================================================================
| VX_generic_stack_WIDTH37_DEPTH3/36 |   8    |   37    |      3       | N  |
=============================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_priority_encoder'. (HDL-193)
Warning:  ../rtl/VX_priority_encoder.v:15: signed to unsigned part selection occurs. (VER-318)
Presto compilation completed successfully.
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__' with
	the parameters "3". (HDL-193)

Inferred memory devices in process
	in routine VX_generic_register_N3 line 21 in file
		'../rtl/VX_generic_register.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      value_reg      | Flip-flop |   3   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'VX_gpr' instantiated from design 'VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__' with
	the parameters "|((N%clk%)(N%reset%)(N%valid_write_request%)(N%VX_gpr_read%I%WORK/VX_gpr_read_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%out_a_reg_data%)(N%out_b_reg_data%))". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_bank_valids' instantiated from design 'VX_priority_encoder_sm_NB7_BITS_PER_BANK3' with
	the parameters "NB=7,BITS_PER_BANK=3". (HDL-193)
Warning:  ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318)
Warning:  ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318)
Warning:  ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318)
Warning:  ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318)
Presto compilation completed successfully.
Information: Building the design 'rf2_128x128_wm1'. (HDL-193)
Warning: Cannot find the design 'rf2_128x128_wm1' in the library 'WORK'. (LBR-1)
Information: Building the design 'VX_cache_data_per_index' instantiated from design 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START11_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END10' with
	the parameters "CACHE_WAYS=2,NUM_IND=32,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,TAG_SIZE_START=0,TAG_SIZE_END=20,IND_SIZE_START=0,IND_SIZE_END=4". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_cache_data_per_index' instantiated from design 'VX_Cache_Bank_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8' with
	the parameters "CACHE_WAYS=2,NUM_IND=32,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,TAG_SIZE_START=0,TAG_SIZE_END=22,IND_SIZE_START=0,IND_SIZE_END=4". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'rf2_32x128_wm1'. (HDL-193)
Warning: Cannot find the design 'rf2_32x128_wm1' in the library 'WORK'. (LBR-1)
Information: Building the design 'VX_generic_priority_encoder' instantiated from design 'VX_cache_data_per_index_CACHE_WAYS2_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4' with
	the parameters "N=2". (HDL-193)
Warning:  ../rtl/VX_generic_priority_encoder.v:22: signed to unsigned part selection occurs. (VER-318)
Presto compilation completed successfully.
Information: Building the design 'VX_cache_data' instantiated from design 'VX_cache_data_per_index_CACHE_WAYS2_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4' with
	the parameters "NUM_IND=32,NUM_WORDS_PER_BLOCK=4,TAG_SIZE_START=0,TAG_SIZE_END=20,IND_SIZE_START=0,IND_SIZE_END=4". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'VX_cache_data' instantiated from design 'VX_cache_data_per_index_CACHE_WAYS2_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4' with
	the parameters "NUM_IND=32,NUM_WORDS_PER_BLOCK=4,TAG_SIZE_START=0,TAG_SIZE_END=22,IND_SIZE_START=0,IND_SIZE_END=4". (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'rf2_32x19_wm0'. (HDL-193)
Warning: Cannot find the design 'rf2_32x19_wm0' in the library 'WORK'. (LBR-1)
Warning: Design 'Vortex' has '6' unresolved references. For more detailed information, use the "link" command. (UID-341)
1
link
Warning: Can't read link_library file 'NanGate_15nm_OCL.db'. (UID-3)

  Linking design 'Vortex'
  Using the following designs and libraries:
  --------------------------------------------------------------------------

Information: Building the design 'rf2_128x128_wm1'. (HDL-193)
Warning: Cannot find the design 'rf2_128x128_wm1' in the library 'WORK'. (LBR-1)
Information: Building the design 'rf2_32x128_wm1'. (HDL-193)
Warning: Cannot find the design 'rf2_32x128_wm1' in the library 'WORK'. (LBR-1)
Information: Building the design 'rf2_32x19_wm0'. (HDL-193)
Warning: Cannot find the design 'rf2_32x19_wm0' in the library 'WORK'. (LBR-1)
Warning: Unable to resolve reference 'rf2_128x128_wm1' in 'VX_shared_memory_block'. (LINK-5)
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_gpr_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__'. (LINK-5)
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4'. (LINK-5)
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4'. (LINK-5)
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (LINK-5)
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (LINK-5)
0
set clk_freq 100
100
set clk_period [expr 100.0 / $clk_freq / 1.0]
1.0
create_clock [get_ports clk] -period $clk_period
Warning: Can't read link_library file 'NanGate_15nm_OCL.db'. (UID-3)
Information: Building the design 'rf2_128x128_wm1'. (HDL-193)
Warning: Cannot find the design 'rf2_128x128_wm1' in the library 'WORK'. (LBR-1)
Information: Building the design 'rf2_32x128_wm1'. (HDL-193)
Warning: Cannot find the design 'rf2_32x128_wm1' in the library 'WORK'. (LBR-1)
Information: Building the design 'rf2_32x19_wm0'. (HDL-193)
Warning: Cannot find the design 'rf2_32x19_wm0' in the library 'WORK'. (LBR-1)
Warning: Unable to resolve reference 'rf2_128x128_wm1' in 'VX_shared_memory_block'. (LINK-5)
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_gpr_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__'. (LINK-5)
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4'. (LINK-5)
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END20_IND_SIZE_START0_IND_SIZE_END4'. (LINK-5)
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (LINK-5)
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (LINK-5)
Warning: Design 'Vortex' has '6' unresolved references. For more detailed information, use the "link" command. (UID-341)
1
set_max_fanout 20 [get_ports clk]
1
set_ideal_network [get_ports clk]
Warning: Design 'Vortex' has '6' unresolved references. For more detailed information, use the "link" command. (UID-341)
1
set_max_fanout 20 [get_ports reset]
1
set_false_path -from [get_ports reset]
Warning: Design 'Vortex' has '6' unresolved references. For more detailed information, use the "link" command. (UID-341)
1
compile -no_map
Warning: Design 'Vortex' has '6' unresolved references. For more detailed information, use the "link" command. (UID-341)
Error: Could not read the following target libraries:
NanGate_15nm_OCL.db 
 (UIO-3)
0
exit

Thank you...