42 lines
977 B
Systemverilog
42 lines
977 B
Systemverilog
`ifndef VX_DCACHE_REQ_IF
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`define VX_DCACHE_REQ_IF
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`include "../cache/VX_cache_define.vh"
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interface VX_dcache_req_if #(
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parameter NUM_REQS = 1,
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parameter WORD_SIZE = 1,
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parameter TAG_WIDTH = 1
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) ();
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wire [NUM_REQS-1:0] valid;
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wire [NUM_REQS-1:0] rw;
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wire [NUM_REQS-1:0][WORD_SIZE-1:0] byteen;
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wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] addr;
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wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
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wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag;
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wire [NUM_REQS-1:0] ready;
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modport master (
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output valid,
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output rw,
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output byteen,
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output addr,
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output data,
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output tag,
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input ready
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);
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modport slave (
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input valid,
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input rw,
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input byteen,
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input addr,
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input data,
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input tag,
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output ready
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);
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endinterface
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`endif |