96 lines
2.9 KiB
Systemverilog
96 lines
2.9 KiB
Systemverilog
`include "VX_platform.vh"
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`TRACING_OFF
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module VX_divider #(
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parameter WIDTHN = 1,
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parameter WIDTHD = 1,
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parameter WIDTHQ = 1,
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parameter WIDTHR = 1,
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parameter NSIGNED = 0,
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parameter DSIGNED = 0,
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parameter LATENCY = 0
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) (
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input wire clk,
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input wire enable,
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input wire [WIDTHN-1:0] numer,
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input wire [WIDTHD-1:0] denom,
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output wire [WIDTHQ-1:0] quotient,
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output wire [WIDTHR-1:0] remainder
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);
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`ifdef QUARTUS
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wire [WIDTHN-1:0] quotient_unqual;
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wire [WIDTHD-1:0] remainder_unqual;
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lpm_divide divide (
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.clock (clk),
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.clken (enable),
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.numer (numer),
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.denom (denom),
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.quotient (quotient_unqual),
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.remain (remainder_unqual)
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);
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defparam
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divide.lpm_type = "LPM_DIVIDE",
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divide.lpm_widthn = WIDTHN,
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divide.lpm_widthd = WIDTHD,
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divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
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divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
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divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
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divide.lpm_pipeline = LATENCY;
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assign quotient = quotient_unqual [WIDTHQ-1:0];
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assign remainder = remainder_unqual [WIDTHR-1:0];
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`else
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reg [WIDTHN-1:0] quotient_unqual;
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reg [WIDTHD-1:0] remainder_unqual;
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always @(*) begin
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begin
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if (NSIGNED && DSIGNED) begin
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quotient_unqual = $signed(numer) / $signed(denom);
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remainder_unqual = $signed(numer) % $signed(denom);
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end
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else if (NSIGNED && !DSIGNED) begin
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quotient_unqual = $signed(numer) / denom;
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remainder_unqual = $signed(numer) % denom;
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end
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else if (!NSIGNED && DSIGNED) begin
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quotient_unqual = numer / $signed(denom);
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remainder_unqual = numer % $signed(denom);
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end
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else begin
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quotient_unqual = numer / denom;
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remainder_unqual = numer % denom;
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end
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end
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end
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if (LATENCY == 0) begin
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assign quotient = quotient_unqual [WIDTHQ-1:0];
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assign remainder = remainder_unqual [WIDTHR-1:0];
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end else begin
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reg [WIDTHN-1:0] quotient_pipe [LATENCY-1:0];
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reg [WIDTHD-1:0] remainder_pipe [LATENCY-1:0];
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for (genvar i = 0; i < LATENCY; i++) begin
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always @(posedge clk) begin
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if (enable) begin
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quotient_pipe[i] <= (0 == i) ? quotient_unqual : quotient_pipe[i-1];
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remainder_pipe[i] <= (0 == i) ? remainder_unqual : remainder_pipe[i-1];
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end
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end
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end
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assign quotient = quotient_pipe[LATENCY-1][WIDTHQ-1:0];
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assign remainder = remainder_pipe[LATENCY-1][WIDTHR-1:0];
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end
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`endif
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endmodule
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`TRACING_ON |