d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
117 lines
3.6 KiB
C++
117 lines
3.6 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <iostream>
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#include <stdlib.h>
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#include <unistd.h>
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#include <math.h>
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#include <assert.h>
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#include <util.h>
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#include "instr.h"
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#include "core.h"
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using namespace vortex;
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Warp::Warp(Core *core, uint32_t warp_id)
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: warp_id_(warp_id)
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, arch_(core->arch())
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, core_(core)
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, ireg_file_(core->arch().num_threads(), std::vector<Word>(core->arch().num_regs()))
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, freg_file_(core->arch().num_threads(), std::vector<uint64_t>(core->arch().num_regs()))
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, vreg_file_(core->arch().num_threads(), std::vector<Byte>(core->arch().vsize()))
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{
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this->reset();
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}
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void Warp::reset() {
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PC_ = core_->dcrs().base_dcrs.read(VX_DCR_BASE_STARTUP_ADDR0);
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#if (XLEN == 64)
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PC_ = (uint64_t(core_->dcrs().base_dcrs.read(VX_DCR_BASE_STARTUP_ADDR1)) << 32) | PC_;
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#endif
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tmask_.reset();
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issued_instrs_ = 0;
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for (uint32_t i = 0, n = arch_.num_threads(); i < n; ++i) {
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for (auto& reg : ireg_file_.at(i)) {
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reg = 0;
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}
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for (auto& reg : freg_file_.at(i)) {
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reg = 0;
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}
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for (auto& reg : vreg_file_.at(i)) {
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reg = 0;
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}
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}
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uui_gen_.reset();
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}
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pipeline_trace_t* Warp::eval() {
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assert(tmask_.any());
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#ifndef NDEBUG
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uint32_t instr_uuid = uui_gen_.get_uuid(PC_);
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uint32_t g_wid = core_->id() * arch_.num_warps() + warp_id_;
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uint32_t instr_id = instr_uuid & 0xffff;
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uint32_t instr_ref = instr_uuid >> 16;
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uint64_t uuid = (uint64_t(instr_ref) << 32) | (g_wid << 16) | instr_id;
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#else
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uint64_t uuid = 0;
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#endif
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DPH(1, "Fetch: cid=" << core_->id() << ", wid=" << warp_id_ << ", tmask=");
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for (uint32_t i = 0, n = arch_.num_threads(); i < n; ++i)
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DPN(1, tmask_.test(i));
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DPN(1, ", PC=0x" << std::hex << PC_ << " (#" << std::dec << uuid << ")" << std::endl);
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// Fetch
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uint32_t instr_code = 0;
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core_->icache_read(&instr_code, PC_, sizeof(uint32_t));
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// Decode
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auto instr = core_->decoder_.decode(instr_code);
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if (!instr) {
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std::cout << std::hex << "Error: invalid instruction 0x" << instr_code << ", at PC=0x" << PC_ << " (#" << std::dec << uuid << ")" << std::endl;
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std::abort();
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}
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DP(1, "Instr 0x" << std::hex << instr_code << ": " << *instr);
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// Create trace
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auto trace = new pipeline_trace_t(uuid, arch_);
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trace->cid = core_->id();
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trace->wid = warp_id_;
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trace->PC = PC_;
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trace->tmask = tmask_;
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trace->rdest = instr->getRDest();
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trace->rdest_type = instr->getRDType();
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// Execute
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this->execute(*instr, trace);
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DP(5, "Register state:");
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for (uint32_t i = 0; i < arch_.num_regs(); ++i) {
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DPN(5, " %r" << std::setfill('0') << std::setw(2) << std::dec << i << ':');
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// Integer register file
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for (uint32_t j = 0; j < arch_.num_threads(); ++j) {
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DPN(5, ' ' << std::setfill('0') << std::setw(XLEN/4) << std::hex << ireg_file_.at(j).at(i) << std::setfill(' ') << ' ');
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}
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DPN(5, '|');
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// Floating point register file
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for (uint32_t j = 0; j < arch_.num_threads(); ++j) {
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DPN(5, ' ' << std::setfill('0') << std::setw(16) << std::hex << freg_file_.at(j).at(i) << std::setfill(' ') << ' ');
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}
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DPN(5, std::endl);
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}
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return trace;
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} |