57 lines
1.3 KiB
Verilog
57 lines
1.3 KiB
Verilog
// `include "../VX_define.v"
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// `include "../Vortex.v"
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`timescale 1ns/1ps
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module vortex_tb (
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);
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reg clk;
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reg reset;
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reg[31:0] icache_response_instruction;
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reg[31:0] icache_request_pc_address;
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// IO
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reg io_valid;
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reg[31:0] io_data;
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// Req
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reg [31:0] o_m_read_addr;
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reg [31:0] o_m_evict_addr;
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reg o_m_valid;
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reg [31:0] o_m_writedata[8 - 1:0][4-1:0];
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reg o_m_read_or_write;
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// Rsp
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reg [31:0] i_m_readdata[8 - 1:0][4-1:0];
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reg i_m_ready;
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reg out_ebreak;
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initial begin
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while (!out_ebreak) begin
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icache_response_instruction = 0;
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end
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end
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Vortex vortex(
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.clk (clk),
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.reset (reset),
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.icache_response_instruction(icache_response_instruction),
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.icache_request_pc_address (icache_request_pc_address),
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.io_valid (io_valid),
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.io_data (io_data),
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.o_m_read_addr (o_m_read_addr),
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.o_m_evict_addr (o_m_evict_addr),
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.o_m_valid (o_m_valid),
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.o_m_writedata (o_m_writedata),
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.o_m_read_or_write (o_m_read_or_write),
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.i_m_readdata (i_m_readdata),
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.i_m_ready (i_m_ready),
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.out_ebreak (out_ebreak)
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);
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always @(clk) #5 clk <= ~clk;
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endmodule |