231 lines
11 KiB
Verilog
231 lines
11 KiB
Verilog
`include "VX_cache_config.v"
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module VX_cache (
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input wire clk,
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input wire reset,
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// Req Info
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input wire [`NUMBER_REQUESTS-1:0] core_req_valid,
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input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr,
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input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_writedata,
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input wire[2:0] core_req_mem_read,
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input wire[2:0] core_req_mem_write,
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// Req meta
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input wire [4:0] core_req_rd,
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input wire [1:0] core_req_wb,
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input wire [`NW_M1:0] core_req_warp_num,
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output wire delay_req,
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// Core Writeback
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input wire core_no_wb_slot,
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output wire [`NUMBER_REQUESTS-1:0] core_wb_valid,
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output wire [4:0] core_wb_req_rd,
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output wire [1:0] core_wb_req_wb,
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output wire [`NW_M1:0] core_wb_warp_num,
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output wire [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata,
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// Dram Fill Response
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_rsp_addr,
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input wire [`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
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output wire dram_fill_accept,
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// Dram request
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output wire dram_req,
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output wire dram_req_write,
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output wire dram_req_read,
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output wire [31:0] dram_req_addr,
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output wire [31:0] dram_req_size,
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output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data
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);
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wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids;
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wire [`NUMBER_BANKS-1:0] per_bank_wb_pop;
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wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid;
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wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd;
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wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb;
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wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num;
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wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data;
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wire dfqq_full;
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wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req;
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wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
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wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_accept;
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wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop;
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wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req;
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wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
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wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data;
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wire[`NUMBER_BANKS-1:0] per_bank_reqq_full;
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assign delay_req = (|per_bank_reqq_full);
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assign dram_fill_accept = (`NUMBER_BANKS == 1) ? dram_fill_accept[0] : dram_fill_accept[dram_fill_addr[`BANK_SELECT_ADDR_RNG]];
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VX_cache_dram_req_arb VX_cache_dram_req_arb(
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.clk (clk),
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.reset (reset),
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.dfqq_full (dfqq_full),
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.per_bank_dram_fill_req (per_bank_dram_fill_req),
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.per_bank_dram_fill_req_addr(per_bank_dram_fill_req_addr),
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.per_bank_dram_wb_queue_pop (per_bank_dram_wb_queue_pop),
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.per_bank_dram_wb_req (per_bank_dram_wb_req),
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.per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr),
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.per_bank_dram_wb_req_data (per_bank_dram_wb_req_data),
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.dram_req (dram_req),
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.dram_req_write (dram_req_write),
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.dram_req_read (dram_req_read),
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.dram_req_addr (dram_req_addr),
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.dram_req_size (dram_req_size),
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.dram_req_data (dram_req_data)
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);
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VX_cache_core_req_bank_sel VX_cache_core_req_bank_sel(
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.core_req_valid (core_req_valid),
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.core_req_addr (core_req_addr),
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.per_bank_valids(per_bank_valids)
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);
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VX_cache_wb_sel_merge VX_cache_core_req_bank_sel(
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.per_bank_wb_tid (per_bank_wb_tid),
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.per_bank_wb_rd (per_bank_wb_rd),
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.per_bank_wb_wb (per_bank_wb_wb),
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.per_bank_wb_warp_num(per_bank_wb_warp_num),
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.per_bank_wb_data (per_bank_wb_data),
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.per_bank_wb_pop (per_bank_wb_pop),
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.core_wb_valid (core_wb_valid),
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.core_wb_req_rd (core_wb_req_rd),
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.core_wb_req_wb (core_wb_req_wb),
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.core_wb_warp_num (core_wb_warp_num),
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.core_wb_readdata (core_wb_readdata)
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);
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generate
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integer curr_bank;
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for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin
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wire [`NUMBER_REQUESTS-1:0] curr_bank_valids;
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wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr;
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wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata;
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wire [4:0] curr_bank_rd;
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wire [1:0] curr_bank_wb;
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wire [`NW_M1:0] curr_bank_warp_num;
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wire [2:0] curr_bank_mem_read;
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wire [2:0] curr_bank_mem_write;
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wire curr_bank_wb_pop;
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wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_wb_tid;
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wire [4:0] curr_bank_wb_rd;
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wire [1:0] curr_bank_wb_wb;
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wire [`NW_M1:0] curr_bank_wb_warp_num;
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wire [31:0] curr_bank_wb_data;
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wire curr_bank_dram_fill_rsp;
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wire [31:0] curr_bank_dram_fill_rsp_addr;
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wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data;
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wire curr_bank_dram_fill_accept;
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wire curr_bank_dfqq_full;
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wire curr_bank_dram_fill_req;
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wire[31:0] curr_bank_dram_fill_req_addr;
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wire curr_bank_dram_wb_queue_pop;
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wire curr_bank_dram_wb_req;
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wire[31:0] curr_bank_dram_wb_req_addr;
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wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data;
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wire curr_bank_reqq_full;
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// Core Req
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assign curr_bank_valids = per_bank_valids[curr_bank];
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assign curr_bank_addr = core_req_addr;
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assign curr_bank_writedata = core_req_writedata;
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assign curr_bank_rd = core_req_rd;
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assign curr_bank_wb = core_req_wb;
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assign curr_bank_warp_num = core_req_warp_num;
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assign curr_bank_mem_read = core_req_mem_read;
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assign curr_bank_mem_write = core_req_mem_write;
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assign per_bank_reqq_full[curr_bank] = curr_bank_reqq_full;
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// Core WB
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assign curr_bank_wb_pop = per_bank_wb_pop[curr_bank];
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assign per_bank_wb_tid [curr_bank] = curr_bank_wb_tid;
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assign per_bank_wb_rd [curr_bank] = curr_bank_wb_rd;
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assign per_bank_wb_wb [curr_bank] = curr_bank_wb_wb;
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assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num;
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assign per_bank_wb_data [curr_bank] = curr_bank_wb_data;
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// Dram fill request
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assign curr_bank_dfqq_full = dfqq_full;
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assign per_bank_dram_fill_req[curr_bank] = curr_bank_dram_fill_req;
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assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr;
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// Dram fill response
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assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
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assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
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assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
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assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept;
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// Dram writeback request
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assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank];
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assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req;
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assign per_bank_dram_wb_req_addr[curr_bank] = curr_bank_dram_wb_req_addr;
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assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data;
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VX_bank bank (
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.clk (clk),
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.reset (reset),
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// Core req
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.delay_req (delay_req),
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.bank_valids (curr_bank_valids),
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.bank_addr (curr_bank_addr),
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.bank_writedata (curr_bank_writedata),
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.bank_rd (curr_bank_rd),
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.bank_wb (curr_bank_wb),
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.bank_warp_num (curr_bank_warp_num),
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.bank_mem_read (curr_bank_mem_read),
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.bank_mem_write (curr_bank_mem_write),
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.reqq_full (curr_bank_reqq_full),
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// Output core wb
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.bank_wb_pop (curr_bank_wb_pop),
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.bank_wb_tid (curr_bank_wb_tid),
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.bank_wb_rd (curr_bank_wb_rd),
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.bank_wb_wb (curr_bank_wb_wb),
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.bank_wb_warp_num (curr_bank_wb_warp_num),
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.bank_wb_data (curr_bank_wb_data),
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// Dram fill req
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.dram_fill_req (curr_bank_dram_fill_req),
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.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
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.dram_fill_req_queue_full(curr_bank_dfqq_full),
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// Dram fill rsp
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.dram_fill_rsp (curr_bank_dram_fill_rsp),
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.dram_fill_addr (curr_bank_dram_fill_rsp_addr),
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.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
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.dram_fill_accept (curr_bank_dram_fill_accept),
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// Dram writeback
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.dram_wb_queue_pop (curr_bank_dram_wb_queue_pop),
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.dram_wb_req (curr_bank_dram_wb_req),
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.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
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.dram_wb_req_data (curr_bank_dram_wb_req_data)
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);
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end
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endgenerate
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endmodule |