Blaise Tine 0a0b28aac0 minor update - 206-214 mhz

2020-08-29 05:14:08 -07:00

..

configs

project directories reorganization

2020-04-14 06:35:20 -04:00

models/memory

RTL code refactoring

2020-04-19 03:38:00 -04:00

modelsim

yosys synthesis refactoring

2020-07-10 18:56:41 -04:00

old_rtl

refactoring fixes

2020-04-14 19:39:59 -04:00

opae

adding using serial divider to save area cost

2020-08-25 02:29:27 -07:00

rtl

minor update - 206-214 mhz

2020-08-29 05:14:08 -07:00

scripts

gpr pipeline optimization

2020-08-01 12:38:30 -04:00

simulate

ibuffer optimization

2020-08-26 04:44:36 -07:00

syn

ibuffer optimization

2020-08-26 04:44:36 -07:00

unit_tests

pipeline refactoring - fmax >= 222 mhz

2020-08-14 21:50:14 -07:00

.gitignore

adding dram writeenable support + scheduler bug fixes

2020-05-27 19:00:23 -04:00

Makefile

lkg build with pipeline + FPU fixes

2020-07-31 09:29:44 -04:00