490 lines
22 KiB
Systemverilog
490 lines
22 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`include "VX_trace.vh"
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module VX_dispatch import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0,
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parameter DOMAIN = WU_DOMAIN_SCALAR
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) (
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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output wire [`PERF_CTR_BITS-1:0] perf_stalls [`NUM_EX_UNITS],
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output wire [`PERF_CTR_BITS-1:0] perf_valids [`NUM_EX_UNITS],
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output wire [`PERF_CTR_BITS-1:0] perf_fires [`NUM_EX_UNITS],
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output wire [`PERF_CTR_BITS-1:0] perf_any_fire_cycles,
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`endif
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// inputs
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VX_operands_if.slave operands_if [`ISSUE_WIDTH],
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// outputs
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VX_dispatch_if.master alu_dispatch_if [`ISSUE_WIDTH],
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VX_dispatch_if.master lsu_dispatch_if [`ISSUE_WIDTH],
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`ifdef EXT_F_ENABLE
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VX_dispatch_if.master fpu_dispatch_if [`ISSUE_WIDTH],
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`endif
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`ifdef EXT_T_ENABLE
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VX_dispatch_if.master tensor_alu_dispatch_if [`ISSUE_WIDTH],
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VX_dispatch_if.master tensor_lsu_dispatch_if [`ISSUE_WIDTH],
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VX_dispatch_if.master tensor_ctrl_dispatch_if [`ISSUE_WIDTH],
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VX_dispatch_if.master tensor_dispatch_if [`ISSUE_WIDTH],
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`endif
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VX_dispatch_if.master sfu_dispatch_if [`ISSUE_WIDTH]
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);
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_PARAM (DOMAIN)
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localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + 1 + `XLEN + `XLEN + `NR_BITS + (3 * `NUM_THREADS * `XLEN) + `NT_WIDTH;
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wire [`ISSUE_WIDTH-1:0][`NT_WIDTH-1:0] last_active_tid;
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wire [`NUM_THREADS-1:0][`NT_WIDTH-1:0] tids;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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assign tids[i] = `NT_WIDTH'(i);
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end
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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VX_find_first #(
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.N (`NUM_THREADS),
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.DATAW (`NT_WIDTH),
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.REVERSE (1)
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) last_tid_select (
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.valid_in (operands_if[i].data.tmask),
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.data_in (tids),
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.data_out (last_active_tid[i]),
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`UNUSED_PIN (valid_out)
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);
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end
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// ALU dispatch
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VX_operands_if alu_operands_if[`ISSUE_WIDTH]();
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wire [`ISSUE_WIDTH-1:0][`NW_WIDTH-1:0] operands_wid;
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wire [`ISSUE_WIDTH-1:0] operands_is_tensor;
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wire [`ISSUE_WIDTH-1:0] tensor_alu_allowed;
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wire [`ISSUE_WIDTH-1:0] tensor_ctrl_allowed;
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wire [`ISSUE_WIDTH-1:0] tensor_wctl_allowed;
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wire [`ISSUE_WIDTH-1:0] tensor_sfu_allowed;
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign operands_wid[i] = wis_to_wid(operands_if[i].data.wis, ISSUE_ISW_W'(i));
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assign operands_is_tensor[i] = operands_wid[i] >= `NW_WIDTH'(`NUM_SCALAR_WARPS);
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assign tensor_alu_allowed[i] = !`INST_ALU_IS_M(operands_if[i].data.op_mod)
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&& !`INST_ALU_IS_RED(operands_if[i].data.op_mod);
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assign tensor_ctrl_allowed[i] = (operands_if[i].data.op_type == `INST_SFU_TMC)
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|| (operands_if[i].data.op_type == `INST_SFU_CSRRS)
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|| (operands_if[i].data.op_type == `INST_SFU_BAR)
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|| (operands_if[i].data.op_type == `INST_SFU_BAR_MASK);
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assign tensor_wctl_allowed[i] = (operands_if[i].data.op_type == `INST_SFU_BAR)
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|| (operands_if[i].data.op_type == `INST_SFU_BAR_MASK);
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assign tensor_sfu_allowed[i] = tensor_ctrl_allowed[i] || tensor_wctl_allowed[i];
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end
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign alu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_ALU) && !operands_is_tensor[i];
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assign alu_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (alu_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) alu_buffer (
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.clk (clk),
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.reset (alu_reset),
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.valid_in (alu_operands_if[i].valid),
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.ready_in (alu_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(alu_operands_if[i].data, last_active_tid[i])),
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.data_out (alu_dispatch_if[i].data),
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.valid_out (alu_dispatch_if[i].valid),
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.ready_out (alu_dispatch_if[i].ready)
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);
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end
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`ifdef EXT_T_ENABLE
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// Tensor INT/control dispatch
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VX_operands_if tensor_alu_operands_if[`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign tensor_alu_operands_if[i].valid = operands_if[i].valid
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&& (operands_if[i].data.ex_type == `EX_ALU)
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&& operands_is_tensor[i]
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&& tensor_alu_allowed[i];
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assign tensor_alu_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (tensor_alu_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) tensor_alu_buffer (
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.clk (clk),
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.reset (tensor_alu_reset),
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.valid_in (tensor_alu_operands_if[i].valid),
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.ready_in (tensor_alu_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(tensor_alu_operands_if[i].data, last_active_tid[i])),
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.data_out (tensor_alu_dispatch_if[i].data),
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.valid_out (tensor_alu_dispatch_if[i].valid),
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.ready_out (tensor_alu_dispatch_if[i].ready)
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);
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end
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`endif
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// LSU dispatch
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VX_operands_if lsu_operands_if[`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign lsu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_LSU) && !operands_is_tensor[i];
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assign lsu_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (lsu_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) lsu_buffer (
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.clk (clk),
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.reset (lsu_reset),
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.valid_in (lsu_operands_if[i].valid),
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.ready_in (lsu_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(lsu_operands_if[i].data, last_active_tid[i])),
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.data_out (lsu_dispatch_if[i].data),
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.valid_out (lsu_dispatch_if[i].valid),
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.ready_out (lsu_dispatch_if[i].ready)
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);
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end
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`ifdef EXT_T_ENABLE
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// Tensor LSU dispatch
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VX_operands_if tensor_lsu_operands_if[`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign tensor_lsu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_LSU) && operands_is_tensor[i];
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assign tensor_lsu_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (tensor_lsu_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) tensor_lsu_buffer (
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.clk (clk),
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.reset (tensor_lsu_reset),
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.valid_in (tensor_lsu_operands_if[i].valid),
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.ready_in (tensor_lsu_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(tensor_lsu_operands_if[i].data, last_active_tid[i])),
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.data_out (tensor_lsu_dispatch_if[i].data),
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.valid_out (tensor_lsu_dispatch_if[i].valid),
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.ready_out (tensor_lsu_dispatch_if[i].ready)
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);
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end
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`endif
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// FPU dispatch
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`ifdef EXT_F_ENABLE
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VX_operands_if fpu_operands_if[`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign fpu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_FPU) && !operands_is_tensor[i];
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assign fpu_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (fpu_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) fpu_buffer (
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.clk (clk),
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.reset (fpu_reset),
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.valid_in (fpu_operands_if[i].valid),
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.ready_in (fpu_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(fpu_operands_if[i].data, last_active_tid[i])),
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.data_out (fpu_dispatch_if[i].data),
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.valid_out (fpu_dispatch_if[i].valid),
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.ready_out (fpu_dispatch_if[i].ready)
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);
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end
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`endif
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// Tensor Core dispatch
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`ifdef EXT_T_ENABLE
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VX_operands_if tensor_operands_if[`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign tensor_operands_if[i].valid = operands_if[i].valid
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&& (operands_if[i].data.ex_type == `EX_TENSOR)
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&& operands_is_tensor[i];
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assign tensor_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (tensor_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) tensor_buffer (
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.clk (clk),
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.reset (tensor_reset),
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.valid_in (tensor_operands_if[i].valid),
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.ready_in (tensor_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(tensor_operands_if[i].data, last_active_tid[i])),
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.data_out (tensor_dispatch_if[i].data),
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.valid_out (tensor_dispatch_if[i].valid),
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.ready_out (tensor_dispatch_if[i].ready)
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);
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end
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`endif
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`ifdef EXT_T_ENABLE
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// Tensor control dispatch
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VX_operands_if tensor_ctrl_operands_if[`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign tensor_ctrl_operands_if[i].valid = operands_if[i].valid
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&& (operands_if[i].data.ex_type == `EX_SFU)
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&& operands_is_tensor[i]
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&& tensor_ctrl_allowed[i];
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assign tensor_ctrl_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (tensor_ctrl_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) tensor_ctrl_buffer (
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.clk (clk),
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.reset (tensor_ctrl_reset),
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.valid_in (tensor_ctrl_operands_if[i].valid),
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.ready_in (tensor_ctrl_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(tensor_ctrl_operands_if[i].data, last_active_tid[i])),
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.data_out (tensor_ctrl_dispatch_if[i].data),
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.valid_out (tensor_ctrl_dispatch_if[i].valid),
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.ready_out (tensor_ctrl_dispatch_if[i].ready)
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);
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end
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`endif
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// SFU dispatch
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VX_operands_if sfu_operands_if[`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign sfu_operands_if[i].valid = operands_if[i].valid
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&& (operands_if[i].data.ex_type == `EX_SFU)
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&& !operands_is_tensor[i];
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assign sfu_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (sfu_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) sfu_buffer (
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.clk (clk),
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.reset (sfu_reset),
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.valid_in (sfu_operands_if[i].valid),
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.ready_in (sfu_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(sfu_operands_if[i].data, last_active_tid[i])),
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.data_out (sfu_dispatch_if[i].data),
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.valid_out (sfu_dispatch_if[i].valid),
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.ready_out (sfu_dispatch_if[i].ready)
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);
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end
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// can take next request?
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign operands_if[i].ready = (alu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_ALU) && !operands_is_tensor[i])
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|| (lsu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_LSU) && !operands_is_tensor[i])
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`ifdef EXT_F_ENABLE
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|| (fpu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_FPU) && !operands_is_tensor[i])
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`endif
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`ifdef EXT_T_ENABLE
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|| (tensor_alu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_ALU) && operands_is_tensor[i] && tensor_alu_allowed[i])
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|| (tensor_lsu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_LSU) && operands_is_tensor[i])
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|| (tensor_ctrl_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_SFU) && operands_is_tensor[i] && tensor_ctrl_allowed[i])
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|| (tensor_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_TENSOR) && operands_is_tensor[i])
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`endif
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|| (sfu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_SFU) && !operands_is_tensor[i]);
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end
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`ifdef SIMULATION
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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`RUNTIME_ASSERT(
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!(operands_if[i].valid && (operands_if[i].data.ex_type == `EX_TENSOR)) || operands_is_tensor[i],
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("%t: *** core%0d-dispatch-illegal-scalar-tensor-op: wid=%0d PC=0x%0h op=0x%0h (#%0d)",
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$time, CORE_ID, operands_wid[i], operands_if[i].data.PC, operands_if[i].data.op_type, operands_if[i].data.uuid)
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)
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`RUNTIME_ASSERT(
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!(operands_if[i].valid && operands_is_tensor[i] && (operands_if[i].data.ex_type == `EX_FPU)),
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("%t: *** core%0d-dispatch-illegal-tensor-fpu-op: wid=%0d PC=0x%0h op=0x%0h (#%0d)",
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$time, CORE_ID, operands_wid[i], operands_if[i].data.PC, operands_if[i].data.op_type, operands_if[i].data.uuid)
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)
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`RUNTIME_ASSERT(
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!(operands_if[i].valid && operands_is_tensor[i] && (operands_if[i].data.ex_type == `EX_SFU) && !tensor_sfu_allowed[i]),
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("%t: *** core%0d-dispatch-illegal-tensor-sfu-op: wid=%0d PC=0x%0h op=0x%0h (#%0d)",
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$time, CORE_ID, operands_wid[i], operands_if[i].data.PC, operands_if[i].data.op_type, operands_if[i].data.uuid)
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)
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`RUNTIME_ASSERT(
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!(operands_if[i].valid && operands_is_tensor[i] && (operands_if[i].data.ex_type == `EX_ALU)
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&& (`INST_ALU_IS_M(operands_if[i].data.op_mod) || `INST_ALU_IS_RED(operands_if[i].data.op_mod))),
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("%t: *** core%0d-dispatch-illegal-tensor-complex-alu-op: wid=%0d PC=0x%0h op=0x%0h mod=0x%0h (#%0d)",
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$time, CORE_ID, operands_wid[i], operands_if[i].data.PC, operands_if[i].data.op_type, operands_if[i].data.op_mod, operands_if[i].data.uuid)
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)
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end
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`endif
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`ifdef PERF_ENABLE
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wire [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_unit_stalls_per_cycle_r;
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wire [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_unit_valids_per_cycle_r;
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wire [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_unit_fires_per_cycle_r;
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_unit_stalls_per_cycle;
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_unit_valids_per_cycle;
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_unit_fires_per_cycle;
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reg [`ISSUE_WIDTH-1:0][`NUM_EX_UNITS-1:0] perf_issue_unit_stalls_per_cycle;
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reg [`ISSUE_WIDTH-1:0][`NUM_EX_UNITS-1:0] perf_issue_unit_valids_per_cycle;
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reg [`ISSUE_WIDTH-1:0][`NUM_EX_UNITS-1:0] perf_issue_unit_fires_per_cycle;
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_stalls_r;
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_valids_r;
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_fires_r;
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reg [`PERF_CTR_BITS-1:0] perf_any_fire_cycles_r;
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|
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for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
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always @(*) begin
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perf_issue_unit_stalls_per_cycle[i] = '0;
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perf_issue_unit_valids_per_cycle[i] = '0;
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perf_issue_unit_fires_per_cycle[i] = '0;
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if (operands_if[i].valid && ~operands_if[i].ready) begin
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perf_issue_unit_stalls_per_cycle[i][operands_if[i].data.ex_type] = 1;
|
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end
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if (operands_if[i].valid) begin
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perf_issue_unit_valids_per_cycle[i][operands_if[i].data.ex_type] = 1;
|
|
end
|
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if (operands_if[i].valid && operands_if[i].ready) begin
|
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perf_issue_unit_fires_per_cycle[i][operands_if[i].data.ex_type] = 1;
|
|
end
|
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end
|
|
end
|
|
|
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for (genvar i=0; i < `NUM_EX_UNITS; ++i) begin
|
|
always @(*) begin
|
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perf_unit_stalls_per_cycle[i] = '0;
|
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perf_unit_valids_per_cycle[i] = '0;
|
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perf_unit_fires_per_cycle[i] = '0;
|
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for (integer isw = 0; isw < `ISSUE_WIDTH; ++isw) begin
|
|
perf_unit_stalls_per_cycle[i] = perf_unit_stalls_per_cycle[i] + perf_issue_unit_stalls_per_cycle[isw][i];
|
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perf_unit_valids_per_cycle[i] = perf_unit_valids_per_cycle[i] + perf_issue_unit_valids_per_cycle[isw][i];
|
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perf_unit_fires_per_cycle[i] = perf_unit_fires_per_cycle[i] + perf_issue_unit_fires_per_cycle[isw][i];
|
|
end
|
|
end
|
|
end
|
|
|
|
// VX_reduce #(
|
|
// .DATAW_IN (`NUM_EX_UNITS),
|
|
// .N (`ISSUE_WIDTH),
|
|
// .OP ("|")
|
|
// ) reduce (
|
|
// .data_in (perf_issue_unit_stalls_per_cycle),
|
|
// .data_out (perf_unit_stalls_per_cycle)
|
|
// );
|
|
|
|
`BUFFER(perf_unit_stalls_per_cycle_r, perf_unit_stalls_per_cycle);
|
|
`BUFFER(perf_unit_valids_per_cycle_r, perf_unit_valids_per_cycle);
|
|
`BUFFER(perf_unit_fires_per_cycle_r, perf_unit_fires_per_cycle);
|
|
|
|
reg perf_any_fire_per_cycle;
|
|
always @(*) begin
|
|
perf_any_fire_per_cycle = 1'b0;
|
|
for (integer i = 0; i < `NUM_EX_UNITS; ++i) begin
|
|
if (perf_unit_fires_per_cycle_r[i] != '0) begin
|
|
perf_any_fire_per_cycle = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
|
|
always @(posedge clk) begin
|
|
if (reset) begin
|
|
perf_stalls_r[i] <= '0;
|
|
perf_valids_r[i] <= '0;
|
|
perf_fires_r[i] <= '0;
|
|
perf_any_fire_cycles_r <= '0;
|
|
end else begin
|
|
perf_stalls_r[i] <= perf_stalls_r[i] + `PERF_CTR_BITS'(perf_unit_stalls_per_cycle_r[i]);
|
|
perf_valids_r[i] <= perf_valids_r[i] + `PERF_CTR_BITS'(perf_unit_valids_per_cycle_r[i]);
|
|
perf_fires_r[i] <= perf_fires_r[i] + `PERF_CTR_BITS'(perf_unit_fires_per_cycle_r[i]);
|
|
perf_any_fire_cycles_r <= perf_any_fire_cycles_r + `PERF_CTR_BITS'(perf_any_fire_per_cycle);
|
|
end
|
|
end
|
|
end
|
|
|
|
for (genvar i=0; i < `NUM_EX_UNITS; ++i) begin
|
|
assign perf_stalls[i] = perf_stalls_r[i];
|
|
assign perf_valids[i] = perf_valids_r[i];
|
|
assign perf_fires[i] = perf_fires_r[i];
|
|
end
|
|
assign perf_any_fire_cycles = perf_any_fire_cycles_r;
|
|
`endif
|
|
|
|
`ifdef DBG_TRACE_CORE_PIPELINE_VCS
|
|
for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
|
|
always @(posedge clk) begin
|
|
if (!reset && ($time > `TRACE_STARTTIME)) begin
|
|
if ((CORE_ID == 0)
|
|
&& alu_dispatch_if[i].valid
|
|
&& ((alu_dispatch_if[i].data.PC == 32'h80000010) || (alu_dispatch_if[i].data.PC == 32'h80000014))) begin
|
|
`TRACE(1, ("%d: core%0d-alu-dispatch-buffer: isw=%0d, valid=%b, ready=%b, wid=%0d, PC=0x%0h, op=0x%0h, mod=%0d, wb=%0d, rd=%0d (#%0d)\n",
|
|
$time, CORE_ID, i, alu_dispatch_if[i].valid, alu_dispatch_if[i].ready,
|
|
wis_to_wid(alu_dispatch_if[i].data.wis, i), alu_dispatch_if[i].data.PC,
|
|
alu_dispatch_if[i].data.op_type, alu_dispatch_if[i].data.op_mod,
|
|
alu_dispatch_if[i].data.wb, alu_dispatch_if[i].data.rd,
|
|
alu_dispatch_if[i].data.uuid));
|
|
end
|
|
if (operands_if[i].valid && operands_if[i].ready) begin
|
|
`TRACE(1, ("%d: core%0d-issue: wid=%0d, PC=0x%0h, ex=", $time, CORE_ID, wis_to_wid(operands_if[i].data.wis, i), operands_if[i].data.PC));
|
|
trace_ex_type(1, operands_if[i].data.ex_type);
|
|
`TRACE(1, (", op="));
|
|
trace_ex_op(1, operands_if[i].data.ex_type, operands_if[i].data.op_type, operands_if[i].data.op_mod, operands_if[i].data.rd, '0, operands_if[i].data.use_imm, operands_if[i].data.imm);
|
|
`TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1_data=", operands_if[i].data.op_mod, operands_if[i].data.tmask, operands_if[i].data.wb, operands_if[i].data.rd));
|
|
`TRACE_ARRAY1D(1, operands_if[i].data.rs1_data, `NUM_THREADS);
|
|
`TRACE(1, (", rs2_data="));
|
|
`TRACE_ARRAY1D(1, operands_if[i].data.rs2_data, `NUM_THREADS);
|
|
`TRACE(1, (", rs3_data="));
|
|
`TRACE_ARRAY1D(1, operands_if[i].data.rs3_data, `NUM_THREADS);
|
|
`TRACE(1, (" (#%0d)\n", operands_if[i].data.uuid));
|
|
end
|
|
end
|
|
end
|
|
end
|
|
`endif
|
|
|
|
endmodule
|