65 lines
1.6 KiB
Verilog
65 lines
1.6 KiB
Verilog
`include "VX_platform.vh"
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module VX_skid_buffer #(
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parameter DATAW = 1
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output reg ready_in,
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input wire [DATAW-1:0] data_in,
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output reg [DATAW-1:0] data_out,
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input wire ready_out,
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output reg valid_out
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);
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reg [DATAW-1:0] buffer;
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reg use_buffer;
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wire push = valid_in && ready_in;
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always @(posedge clk) begin
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if (reset) begin
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use_buffer <= 0;
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valid_out <= 0;
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end else begin
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if (push && (valid_out && !ready_out)) begin
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assert(!use_buffer);
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use_buffer <= 1;
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end
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if (ready_out) begin
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use_buffer <= 0;
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end
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if (push) begin
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buffer <= data_in;
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end
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if (!valid_out || ready_out) begin
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valid_out <= valid_in || use_buffer;
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data_out <= use_buffer ? buffer : data_in;
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end
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end
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end
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assign ready_in = !use_buffer;
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/*wire empty, full;
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VX_generic_queue #(
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.DATAW (DATAW),
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.SIZE (2),
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.BUFFERED (0)
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) queue (
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.clk (clk),
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.reset (reset),
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.push (valid_in),
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.pop (ready_out),
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.data_in(data_in),
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.data_out(data_out),
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.empty (empty),
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.full (full),
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`UNUSED_PIN (size)
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);
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assign ready_in = ~full;
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assign valid_out = ~empty;*/
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endmodule |