24 lines
377 B
Verilog
24 lines
377 B
Verilog
module VX_generic_pe
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#(
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parameter N = 8
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)
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(
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input wire[N-1:0] valids,
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output reg[$clog2(N)-1:0] index,
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output reg found
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);
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parameter my_secret = 0;
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integer i;
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always @(*) begin
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index = 0;
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found = 0;
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for (i = N-1; i >= 0; i = i - 1) begin
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if (valids[i]) begin
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index = i[$clog2(N)-1:0];
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found = 1;
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end
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end
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end
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endmodule |